Defect Inspection Equipment

Using laser-based patterned-wafer inspection for memory and logic applications

Developed for 0.18-µm design rules, an inspection tool features improved software algorithms, fast scan and data-processing electronics, and enlarged collection areas.

Thomas Reuter and Ulrike Böhmler, Infineon Technologies; and Matthew McLaren and Siqun Xiao, KLA-Tencor

As design rules continue to shrink, the demand increases for effective inspection tools to detect defects that affect device yields. From front-end-of-line (FEOL) trench etch and interconnect formation steps to back-end-of- line (BEOL) metal etch steps, defects are generated that can disable devices and lead to yield losses. To meet the challenge of defect detection and reduction on ever-smaller devices, the AIT II, a next-
generation patterned-wafer inspection tool from KLA-Tencor (San Jose), was installed at Infineon Technologies (formerly Siemens Microelectronics Center, or SIMEC) in Dresden, Germany, in July 1998. Fully integrated into the production line, the tool is used in both memory and logic applications across the entire process flow.

This article focuses on an investigation that was conducted to determine the AIT II's production worthiness, its applicability to IC production, and its advantages over its predecessor, the AIT I. During the study, inspection recipes were created for a range of IC products. The article summarizes data collected from 64- and 256-Mb memory applications, including front-end capacitor and isolation trench formation, tungsten CMP, and metal etch processes. In addition, data from the inspection of logic products, such as barrier metal deposition and second and third metal etch steps, are presented. Finally, the tool's throughput and availability are discussed. The results of the study are presented in three sections: memory applications; logic applications; and throughput, availability, and uptime. Each section presents and discusses data from specific inspection applications to assess the tool's overall performance.

Tool Capabilities

Based on the AIT I platform, the AIT II uses low-angle laser illumination and dark-field collection optics. While drawing on the design of its predecessor, the new inspection tool offers enhanced sensitivity and throughput. Developed to meet the inspection requirements of 0.18-µm design rules and extendable down to 0.13 µm, the tool features improved software algorithms, faster scan and data-processing electronics, and enlarged collection areas on each of its two collection channels to promote improved defect sensitivity. The system also offers an optional multiple-spot-size feature that provides for enhanced sensitivity but has the drawback of decreasing throughput.

The tool's software improvements provide enhanced postscan data processing, permitting the assignment of region-based detection thresholds defined by the user during recipe setup. This allows the tool to inspect both repeating array and peripheral bus-connection areas simultaneously without compromising sensitivity in either region. Improvements in the system's scan and data-processing electronics contribute to an overall throughput improvement of approximately 30%.While all the recipes designed for this study used the region-based multithresholding feature, only the default spot size of 10 µm was used during the evaluation.

Memory Applications

For the purposes of this study, the AIT II was used to investigate three memory products: a 256-Mb DRAM device, a 64-Mb device with a design rule of 0.25 µm, and a 64-Mb device with a design rule of 0.20 µm. In each case, a production-worthy recipe setup was emphasized, which enabled the tool's subsequent trouble-free integration into the production flow as part of an in-line defect-monitoring strategy. When performing investigations of memory product, emphasis was placed on detecting metal shorts in both the array and the periphery regions.

FEOL Isolation Trench Formation--256-Mb DRAM. Following the isolation trench etch step and thermal oxidation, the 256-Mb DRAM product was inspected. The tool successfully detected some extremely subtle deformations in the trench structures that were probably related to a focus problem during resist exposure before isolation trench etch. These very low-scattering defects, shown in Figure 1, include sub-0.1-µm variations in the sidewalls of the isolation trench structures.

Figure 1: SEM micrographs showing sub-0.1-µm defects in the formation of the isolation trenches of a 256-Mb device following isolation trench etch and thermal oxidation.

BEOL local interconnect CMP--256-Mb DRAM. To optimize a dual-damascene tungsten CMP process for 256-Mb DRAM production by detecting critical CMP defects, an inspection routine was performed immediately after local interconnect tungsten planarization. While the inspection revealed that the majority of defects were slurry residuals, approximately 10—20% of the defects detected in the cell array were faint microscratches with a very low-scattering signature. As illustrated in Figure 2, further investigation using scanning electron microscopy (SEM) techniques revealed that some of the scratches in the cell array "smeared" the local interconnect tungsten lines, causing metal shorts that were detected during electrical testing.

Figure 2: Optical image of a local interconnect tungsten CMP scratch in the cell array of a 256-Mb DRAM device (left) and an SEM image of this defect showing "smearing" of the tungsten lines along the axis of the scratch (right).

FEOL Deep Trench Etch--0.25-µm, 64-Mb DRAM. Another test of the inspection tool was conducted after polysilicon recess etch and deep trench etch. On one wafer, defects that appeared within the trench structures were detected and subsequently characterized as the result of overetching the trench walls. SEM images of these defects are shown in Figure 3. The low-angle illumination used by the inspection tool to minimize sensitivity to process variation is not limited to the detection of surface structures; as demonstrated in the study, defects actually within the trench structures can be detected as well.

Figure 3: SEM micrographs of defects in the capacitor trenches of a 0.25-µm, 64-Mb DRAM device after polysilicon recess etch.

BEOL Postmetal 1 Etch--0.25- and 0.20-µm, 64-Mb DRAM. Post—metal etch inspection showed that the tool was more sensitive than its predecessor in inspecting both the array and periphery regions. This is a result largely of the tool's ability to perform region-based optimization, which permits full-die area inspections without compromising sensitivity. Extra metal-forming bridges in the bus and array regions, the principal defects of interest, were caused predominantly by masking during resist exposure before metal etch. Typical examples of this defect type are depicted in Figure 4. While the earlier inspection tool could detect defects in periphery bus areas, including metal bridges, detection was achieved at the cost of compromising overall recipe sensitivity. The new system's region-based parameter optimization enables optimal detection sensitivity in all die regions with minimal risk of nuisance or false alarms.

Figure 4: Optical images of a 0.25-µm, 64-Mb DRAM device (left) and a 0.20-µm, 64-Mb DRAM device (right) showing metal-forming bridges in the bus and array regions detected after metal 1 etch.

Logic Applications

To determine the ability of the new inspection tool to inspect logic applications, a 0.25-µm device was used. Full-die inspections were carried out and recipes were optimized for in-line process monitoring while maintaining robust, repeatable performance with minimal false or nuisance alarms.

Titanium Barrier Anneal--0.25-µm Logic Device. An inspection recipe was created so that the tool could monitor the 0.25-µm logic process following the anneal of the titanium barrier layer before contact deposition. Region-based contrast and threshold settings were used to ensure maximum sensitivity over the full die. The SEM micrographs in Figure 5, showing a small particle detected amid repeating logic structures, provides an example of the tool's sensitivity.

Figure 5: SEM image and magnification showing sub-0.1-µm defects between logic structures on a 0.25-µm device after titanium barrier layer anneal.

Metal 2 and 3 Postetch Inspections--0.25-µm Logic Device. Inspection recipes following metal 2 and 3 etch were produced that again took advantage of the tool's ability to optimize detection thresholds on a per-region basis while permitting full-die inspections. Optical images of typical defects, captured using the tool's onboard review capabilities, are illustrated in Figures 6 and 7. Figure 6 shows metal shorts in the horizontal metal 2 lines located in the periphery bus structures. The image on the right shows continuing evidence of a residual particle masking the metal etch process, causing the bridging defect. Examples of metal 3 defects, again located in the bus structures, are depicted in Figure 7. While it is clear that in some cases these defects are large (>10 µm), their location over multilayer metal interconnects and in areas where metal grain is clearly visible poses additional challenges to laser inspection technology. Tolerance to high-scattering background features, local variations, and nuisance defects is essential. The inspection tool demonstrated that it is able to distinguish yield-critical defects in these regions.

Figure 6: Optical images of shorts in the horizontal metal 2 lines of a 0.25-µm logic device in the periphery bus structures. Right-hand image shows continuing evidence of a residual particle masking the metal etch process, causing the bridging defect.

Figure 7: Optical images of metal 3 defects located in the periphery bus regions of a 0.25-µm logic device after metal 3 etch.

Throughput, Availability, and Uptime

The throughput of the tool in wafers per hour was measured on two 64-Mb DRAM product wafers using only the 10-µm spot size. FEOL deposition and BEOL interlevel contact etch layers were inspected. In each case the wafer edge exclusion was set to 3 mm, and each cycle involved a full-wafer inspection using a production-ready recipe. For the FEOL deposition inspection, a throughput of 36.8 wafers/hr was measured based on the full inspection of a 25-wafer lot. For the BEOL contact etch layer a throughput of 35.2 wafers/hr was measured based on the inspection of a 6-wafer lot.

Figure 8: Breakdown of the inspection tool's availability and usage during a nine-month period.

The availability and usage of the inspection tool has been tracked since it was released into production in October 1998. Its utilization has increased steadily to approximately 80% of production time, while the remaining 20% has been allocated to engineering work. In the period since the investigation ended and the tool was installed on the production floor, there have been a total of six recorded failures involving four independent issues and two instances of operator intervention. Total downtime has accounted for less than 0.18% of available tool time. Figure 8 presents a breakdown of tool availability and usage.

Conclusion

The AIT II has been evaluated on a range of IC products on-site at Infineon Technologies. It has been used to inspect a range of process layers on both memory and logic products, covering the full process flow from the front end to the back end of the line. The tool can capture critical defects both at the trench etch level and over multilevel metal structures. The key to BEOL inspection performance has been the application of region-based detection threshold optimization, which permits full-die inspections without compromising sensitivity in any particular region. Since its release into full production, the tool has demonstrated a high degree of technical maturity and reliability, having experienced only six failures during more than nine months of use. Memory product inspections have been released for production use while the investigation of logic applications continues.

Acknowledgments

The article was first presented at the 1999 Advanced Semiconductor Manufacturing Conference and Workshop sponsored by the Institute of Electrical and Electronics Engineers and SEMI, September 8—10, 1999, in Boston and was originally published in the conference proceedings. Used with permission. The authors would like to thank Simone Steck of Infineon Technologies (Dresden, Germany) and Rebecca Howland Pinto of KLA-Tencor (San Jose) for their contributions to this article.

Thomas Reuter is a process engineer in the defect reduction group at Infineon Technologies in Dresden, Germany, where he is responsible for BEOL defect monitoring for both DRAM and logic technologies. Reuter began his career at Texas Instruments Germany as a failure analysis engineer before joining Siemens Microelectronics (now Infineon Technologies) in 1996. He has a diploma in microelectronic technology from the technical college in Mittweida, Germany, and has coauthored several papers on patterned-wafer inspection applications. (Reuter can be reached at +49 351 8862524 or thomas.reuter@infineon.com.)

Ulrike Böhmler is a process engineer in the defect reduction group at Infineon Technologies, where she is responsible for defect monitoring in the mid-of-line processes for DRAM and logic technologies. She has been employed at the facility since 1995, originally working in the CMP process group before joining the defect reduction team about two years ago. Previously, Böhmler spent five years at Gould Electronics as a process engineer in the physical-chemical development and analysis lab. Böhmler graduated from the technical college in Aalen, Germany, as a material science engineer. (Böhmler can be reached at +49 351 8862414 or ulrike.boehmler@infineon.com.)

Matthew McLaren, PhD, is an applications engineer at KLA-Tencor (San Jose), where he has focused on implementing patterned-wafer inspection solutions at sites across Europe. Before joining the company in 1997, he was a development engineer in the implant division of Applied Materials, working on defect and contamination reduction and developing beam transport optics. McLaren has authored papers on defect reduction studies, ion beam—induced deposition, and thin-film growth models. He received his PhD in 1996 from the University of Salford in Manchester, UK, for research into ion beam—induced metal deposition. (McLaren can be reached at +44 118 9365700 or matthew.mclaren@kla-tencor.com.)

Siqun Xiao, PhD, is a product applications specialist for the AIT product line at KLA-Tencor. His expertise is in the field of wafer inspection and defect detection. Before joining KLA-Tencor, he worked in the field of electron microscopy and IC device failure analysis. He received his PhD in physics from Göttingen University, Germany. (Xiao can be reached at 408/875-4684 or siqun.xiao@kla-tencor.com.)

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