Building Copperopolis

Enabling low-k material integration through low-ion plasma dry strip processes

Qingyuan Han and Ivan L. Berry, Eaton Semiconductor; and Jianou Shi, Thomas W. Mountsier, and Mary Anne Plano, Novellus Systems

Postdielectric dry strip and residue removal are critical steps toward integrating low-k dielectrics into damascene or dual-damascene processes.

As design rules go below 0.18 µm, interconnect delay becomes the main source of overall device delay for silicon dioxide/aluminum architectures.¹ Because resistance-capacitance (RC) delay directly limits device speed, the semiconductor industry has been prompted to adopt new materials and architectures. Low-k dielectric/copper damascene and dual-damascene are now beginning to replace traditional SiO_²/aluminum subtractive etch architectures and process flows. The dual-damascene architectures have largely been implemented in half steps. While aiming to implement low-k/copper in their production processes, some chipmakers have first adopted SiO_²/copper and others have adopted low-k/aluminum architectures. In the process of moving toward full low-k/copper dual-damascene flows, manufacturers have identified new integration challenges posed by the removal of photoresist and postetch residues.²

One significant challenge involves dry photoresist strip processes. Because the chemical structure of many low-k materials differs from and is less passive than that of the conventional SiO^₂ dielectric, dry strip processes can cause unacceptable undercutting (insufficient selectivity) and fundamentally alter low-k film properties. Consequently, there has been renewed interest in solving problems associated with dry strip and in developing specialized, integrated dry photoresist/residue removal processes that provide high selectivity while leaving the k value or mechanical properties of the low-k dielectric unaffected. This article explores the dry strip integration issues of Coral low-k film developed by Novellus Systems (San Jose) and describes the development and results of specialized, low-ion plasma dry resist/residue removal processes. In collaboration with Lam Research (Fremont, CA), which has developed anisotropic etch processes, and Eaton (Beverly, MA), which has created dry strip processes, Novellus has built dual-layer copper damascene structures using low-k film as the dielectric material.

Low-k Materials and Selectivity

Novellus's CVD-deposited insulator, or low-k dielectric, uses the carbon doping of silicon dioxide to form an SiO^₂-like material with a reduced dielectric constant (k value). The Coral family of low-k films in the study under investigation are thermally stable to 500°C, have a dielectric constant of 2.7, decrease power dissipation, reduce line-to-line capacitance, and minimize crosstalk. Figure 1 shows a cross section of a single-layer copper damascene structure with this low-k film.

Figure 1: Cross section of a single-layer copper damascene structure with low-k film after trench fill. (1 = cap layer, 2 = copper, 3 = low-k film, 4 = etch stop, and 5 = silicon substrate).

However, the use of low-k materials complicates the stripping process. Historically, resist stripping has been viewed as a noncritical step largely because of the inherently high selectivity of photoresist to SiO^₂ and the minuscule interaction of the stripping process with the SiO^₂ of the SiO^₂/aluminum architecture. This has permitted extensive overashing and very wide process windows. Dry stripping techniques, while highly viable for removing resist from low-k materials, require much greater process control and optimization when used in the copper damascene process than when used in traditional SiO^₂/aluminum processes. A key problem for most low-k films, and especially organic-based materials, is that strip selectivity is problematic. Conventional dry strip processes used for low-k films create unacceptable undercutting and typically result in a selectivity of only 2:1 or 3:1 compared to typical selectivities of >100:1 for SiO^₂/aluminum architectures.

Figure 2: SEM micrographs showing devices in the postetch, prestrip condition (top); after partial ash removal with a traditional oxygen strip (middle); and after a specialized dry strip process (bottom). (1 = photoresist, 2 = antireflective layer, 3 = hard mask, and 4 = organic low-k material).

Although doped silicon structures offer higher inherent plasma resistance than organic-based low-k films, all low-k materials are characterized by much greater susceptibility to oxygen plasma species than SiO^₂. Figure 2 compares the selectivity performance achieved by the use of a traditional oxygen strip process and that achieved by the use of a specialized dry strip process. The SEM images depict an organic spin-on low-k material, which offers less plasma resistance than Coral and thus dramatically highlights strip sensitivity. In this embedded hard-mask damascene architecture, the low-k material is beneath an SiO^₂ or Si^₃N^₄ hard mask, which is itself beneath an antireflective coating, which is covered by patterned photoresist. A conventional oxygen plasma discharge was first used to strip the photoresist. The isotropic strip process, with a photoresist to low-k selectivity ratio of approximately 3:1, removed a significant amount of the underlying low-k material, which is clearly unacceptable for device manufacturing. Exacerbating the selectivity issue, the photoresist was hardened by the process, producing ever-diminishing selectivity.

Even for highly sensitive organic low-k materials, the selectivity issue can be solved by implementing an optimized dry strip process. This is achieved by using an almost purely chemical plasma with a low-ion content instead of the plasma discharge method with a typical plasma used for dry strip. The activation energy for the reaction of different polymers varies, depending on catalysis by ions. This variation has historically been used to achieve selectivity in the etch process of one polymer over another.³ By minimizing the ion content of the plasma, selectivity can be increased to well over 10:1.

Preserving Low-k Properties

Because doped silicon oxide structures offer higher plasma resistance than organic low-k films, their strip selectivity is somewhat less problematic. While doped silicon oxide films are not substantially etched by conventional oxygen-based, dry resist strip processes, the Si-CH^₃ and Si-C bonds in the film are readily susceptible to attack by the active oxygen species of the dry strip plasma discharge. In the presence of oxygen radicals, these bonds are broken and replaced by Si-O bonds, resulting in a more SiO^₂-like film with a higher dielectric constant. The loss of the Si-CH^₃ and Si-C bonds also increases the film's refractive index and film stress, which is often high enough to crack the film. To prevent the oxygen degradation of low-k films, oxygen-free plasmas have been used successfully for organic and doped oxide low-k materials.^2,4 Both organic and doped silicon oxide films require a common process solution that addresses selectivity and the ability to strip without altering the k value.

This study investigated the characteristics of doped silicon oxide films when they were dry stripped with three different plasma chemistries: oxidizing, reducing, and fluorinated plasmas. Data from earlier studies indicated that the presence of ionizing radiation in the strip process can increase the plasma attack rate of many low-k materials.⁵ Empirically, the same effects were observed in doped silicon oxide films. The best results for all three processes were obtained by using a low-ion plasma—that is, a plasma with a reduced ion/electron content. In two of the processes, this type of plasma did not cause a substantial change in k value or an observable removal of the low-k film. (Measurements of the k value had not yet been obtained on fluorinated plasma processes.) All three processes resulted in clean dual-damascene structures without measurable residues. In many cases, even a typical post-dry-strip DI-water rinse was not required.

Dry Strip Experiments

Experiments were performed using Eaton's FusionGemini ES (enhanced strip) downstream microwave plasma asher. This tool is designed to achieve high selectivity between photoresist and low-k materials and can be used for Coral as well as other organic and inorganic low-k formulations. Table I lists low-k materials for which high-selectivity, low-damage dry strip processes have been developed.

Type of Low-k Material	Low-k Material	Selectivity Ratio (photoresist to Low-k)
Organic	BCB	>10:1
	Flare	>10:1
	SiLK	>10:1
	Parylene AF4	>10:1
Doped oxide	Coral	>20:1
	HOSP	>20:1
	HSQ (FOx-15, 17)	>20:1

Table I: List of low-k materials for which high-selectivity, low-damage dry strip processes using a plasma with a low-ion content have been developed.

The tool enables highly selective strip processes over low-k materials because it combines downstream microwave plasma and radiant wafer heating. Its radiant heating ability and consequent rapid temperature ramp rate permit multiple-temperature operation within a recipe, thereby providing a very efficient temperature for each process segment. A low-damage microwave plasma source and delivery design that reduces or eliminates all sources of ionizing radiation is essential to high-selectivity, low-damage, low-k processes.⁵ These combined features permit comprehensive dry strip and residue removal over low-k films without altering the films' characteristics.

Figure 3: Postetch SEM micrograph before ash/residue removal. (1 = photoresist, 2 = low-k film, 3 = etch stop)Image courtesy of LAM Research

Figure 4: SEM micrographs showing a silicon doping trench structure before the ashing process (left) and after resist strip and residue removal (right) (1 = photoresist, 2 = sidewall polymer, 3 = low-k film).

The central challenge in the strip process is to remove a thick sidewall polymer that is characteristic of the highly selective etch process. The SEM micrograph in Figure 3 shows about 4–5 kÅ of deep ultraviolet (DUV) resist that remain on top of the device features after low-k etch and before strip. The SEM images in Figure 4 highlight device features before and after the removal of the thick sidewall polymer and other heavy postetch residues. The removal of the resist, which strips more quickly than the sidewall residue, can exacerbate problems associated with strip selectivity. Meeting this selectivity challenge is a key objective in the strip process.

Three optimized processes were examined for their ability to strip the resist without damage to the doped silicon:

• Process 1—hydrogen-based reducing plasma.

• Process 2—fluorine-based plasma.

• Process 3—oxygen-based plasma.

Each of these processes was optimized to a first order for pressure, temperature, gas flow, and gas composition. Samples for this study included DUV blanket-coated wafers, Coral blanket-coated wafers, and patterned wafers for residue removal analysis. All samples were on 200-mm wafers. The film thicknesses were measured before and after exposure to the plasma by means of ellipsometry to determine the etch rate of the doped film and to measure its refractive index. The etch rate of the low-k doped film was determined as the total loss of doped film divided by the resist removal time for each process. The resist strip rate was calculated as the total initial resist thickness divided by the time required to remove the resist. To save optimization time, the doped film etch rates were measured only at a single process temperature. To determine ash selectivity, the doped film etch rate was compared to the measured strip rate of blanket-coated resist processed under the same strip conditions.

The reflective indices of the film were measured partly to study the effect of plasma exposure and partly as a high-precision measure of the postexposure thickness. Stress measurements were also used to evaluate the films' integrity and cracking potential. Fourier transform infrared (FTIR) measurements were used to study the effect of the strip process on the chemical bonds. Finally, the best overall processes were selected for further k-value measurements. Table II summarizes the results of several process runs.

	Stress Change (E9, dyne/cm2)	Refractive Index	FTIR Peak Ratio (%)	Dielectric Constant (±0.03)	Selectivity Ratio
Low-k film	—	1.428	43	2.70	—
Process 3 (oxygen based, conventional plasma)	High	Not measured	Low	Not measured	>10:1
Process 3 (oxygen based, low-ion plasma)	0.01	1.431	43	2.74	>20:1
Process 2 (fluorine based, low-ion plasma)	Not measured	1.425	Not measured	Not measured	>30:1
Process 1 (reducing plasma, low-ion plasma)	0.05	1.427	40	2.73	>90:1

Table II: List of film properties before and after various dry strip processes.

Experimental Results

Under traditional strip conditions at a temperature of 270°C, process 3 produced a DUV-strip-to-film-etch selectivity ratio of approximately 10:1. However, the poststrip stress measured on the film was high and the FTIR peak ratios were rather low because of the removal of many surface Si-CH^₃ bonds. By performing process 3 with a low-ion plasma, a selectivity ratio of >20:1, low film stress, high FTIR peak ratios, and an insignificant change in the k value were achieved. Positive results were also obtained with low-ion plasma for the other two processes. Figure 5 shows the strip rate and selectivity for all three processes.

Figure 5: Low-ion plasma dry strip rates of DUV photoresist versus temperature for three processes compared to etch rates of doped silicon low-k film under the same conditions.

The use of the low-ion plasma technique to strip low-k films results in strip rates somewhat lower than those for conventional strip techniques. However, since far less resist remains on the dual-damascene architecture after etch than on traditional subtractive etch structures, the two methods entail similar process times. Even the time required to accomplish the reducing plasma process, which has the lowest strip rate, can be optimized to completely remove resist in <60 seconds, during which time the doped silicon film sustains insignificant or no damage. Consequently, low-ion plasma strip processes for dual-damascene structures complement the productivity of the downstream microwave plasma asher.

Figure 6: FTIR spectra of doped silicon film before and after low-ion plasma dry strip using the reducing plasma process (process 1).

Figure 6 shows an FTIR spectrum of the doped silicon film before and after dry strip using the reducing plasma process. All major chemical bonds remain unchanged. Table II lists stress, refractive index, FTIR peak ratio, dielectric constant, and dry strip selectivity before and after 60 seconds of dry strip processing on the blanket films by the three different dry strip processes. (Some film properties for process 2 had not yet been measured.) None of the three processes significantly affects the properties of the doped silicon film.

Postetch Residue Removal

In conventional subtractive metal etch process flows, there is a trend toward phasing out wet strip techniques as dry strip processes are being increasingly used for both resist and residue removal. This approach eliminates the significant cost of a wet strip step and the related use of hazardous chemicals. In advanced dry strip processes, resist and residue removal are integrated within a single process step.

To investigate the ability of the low-ion plasma dry strip process to remove postetch residues, process 1, the least aggressive method, was used to remove all etch residues and sidewall polymers. The reducing chemistry selectively removed these polymers and DUV resist without causing undercutting into the low-k material, leaving clean sidewalls after dry strip. The SEM cross section of the single-damascene Coral copper process illustrated in Figure 1 reveals that low-k trenches are completely filled with copper after stripping and cleaning, indicating that all of the residue was removed. These results show that the dry strip and residue removal process eliminated the need for and the cost of the follow-on steps of wet chemical strip and DI-water rinse.

Conclusion

Postdielectric dry strip and residue removal have become critical steps in the integration of low-k dielectrics into damascene or dual-damascene processes. While a wide variety of low-k materials are in development, all such materials generally will be vulnerable to undercutting or degradability by conventional resist strip and residue removal processes if techniques are not developed to counteract these tendencies. When stripped by conventional means, low-k materials can degrade, causing increasing film stress, a loss of mass, a changed refractive index, and an increased dielectric constant.

Highly selective dry strip processes have been developed that will not alter the properties of doped silicon films. Dry strip and residue removal by means of low-ion plasma resulted in minimal film degradation in the three process chemistries under investigation. The oxygen-free, reducing plasma had the least significant impact on the properties of low-k films, followed by the fluorine plasma. The oxygen-based plasma, which caused the greatest alteration in dielectric material, had a k-value change of only 1.5%.

Low-ion plasma dry strip processing techniques are being adopted as fabs begin to use low-k materials. Initial attempts to simply extend traditional SiO^₂/aluminum processes to use in low-k flows have proven unsuccessful. However, low-ion plasma dry strip tools can be employed for both SiO^₂/aluminum and copper/low-k architectures, enabling fabs to run markedly different processes on a single tool and to span significantly different device generations. This is a potentially low-cost, low-risk path to the implementation of low-k dielectrics in production environments.

Acknowledgments

The authors would like to express their gratitude to Sematech and Lee Tye from Sematech for assistance in preparing BCB, Flare, and SiLK wafers for evaluation. They also wish to thank Pabni Sakthivel, Stuart Rounds, and Ricky Ruffin of Eaton for their process expertise and efforts in reviewing the results of the study presented here and Graham Cable and Peter Gillespie of Eaton for their support in producing this paper.

References

1. MT Bohr, "Interconnect Scaling—The Real Limiter to High Performance ULSI," in Proceedings of the IEEE International Electron Devices Meeting (New York City: The Institute of Electrical and Electronics Engineers, 1995), 241—242.

2. I Morey and A Asthana, "Etch Challenges of Low-k Dielectrics," Solid State Technology 42, no. 6 (1999): 71—78.

3. R d'Agostino, Plasma Deposition Treatment and Etching of Polymers (New York: Academic Press, 1990).

4. D Louis et al., "Resist Removal Process in Dual Damascene Structure Integrating Cu and SiLK for 0.18-µm Technology" (paper presented at MNE 99, Rome, September 1999).

5. Q Han et al. "Achieving Highly Selective Resist Strip and Residue Removal Over Low-k Dielectrics," Future Fab International 7 (1999): 219—222.

Qingyuan Han, PhD, is a senior process engineer at Eaton's Fusion Systems Division in Rockville, MD. A project leader responsible for low-k film process development, he has developed strip and residue removal processes for several low-k materials. Han has authored several papers on semiconductor processing and more than 10 papers on the plasma CVD of diamond films and the plasma treatment of chemical waste. He holds multiple patents related to semiconductor processing. He has an MS and a PhD from the University of Minnesota (Twin Cities) in mechanical engineering. (Han can be reached at 301/251-0300 or qhan@fusn.com.)

Ivan L. Berry is the director of process technology at Eaton's Fusion Systems Division and manages process technology development and customer process support. Before joining Eaton, he focused on developing ion projection lithography and was one of the founders of the Advanced Lithography Group consortium. He has worked in semiconductor processing for more than 20 years and was an early pioneer in focused ion beam technology. Berry, a member of IEEE, AVS, and SPIE, has authored and presented many articles on semiconductor processing and ion beam technologies. He received a BSEE from Drexel University in Philadelphia and an MS in applied physics from Johns Hopkins University in Baltimore. (Berry can be reached out 301/251-0300 or iberry@fusn. com.)

Jianou Shi, PhD, is a manager of low-k film development at Novellus Systems, San Jose, where he has also worked on parylene and HDP Speed. Before joining Novellus he was a senior scientist and Asian marketing manager for Fusion Semiconductor Systems, a senior engineer for Diablo Research, a research associate in the material science department of Pennsylvania State University, and a faculty member at Fudan University in Shanghai. Shi is the author of many articles on plasma and semiconductor processing. He received his PhD in materials science and physical engineering from Pennsylvania State University in State College and his MS in electrical engineering from Dartmouth College in Hanover, NH. (Shi can be reached at 408/943-9700 or jianou.shi@novellus.com.)

Thomas W. Mountsier is the manager of low-k integration at Novellus Systems, where he is responsible for all aspects of integrating the Coral family of films. In the more than 10 years he has spent at Novellus, he has been involved with several CVD products, including PECVD dielectrics, CVD tungsten, and HDPCVD dielectrics. Mountsier has authored several papers on CVD applications and holds two patents related to CVD processing. Before joining Novellus he was a process engineer at an advanced manufacturing facility operated by Signetics (now Philips Semiconductor). He received his BS in chemical engineering from Purdue University in West Lafayette, IN. (Mountsier can be reached at 408/943-9700 or thomas.mountsier@novellus.com.)

Mary Anne Plano, PhD, is the low-k program manager at Novellus, where she focuses on carbon-doped oxide PECVD film. She has spent the last four years at Novellus developing CVD low-k films. Before joining Novellus she worked on CVD diamond at Crystallume, managing an electronic applications group. While there she worked on high-mobility diamond detectors and diamond JFET transistors. Plano has a BS in physics from the University of Michigan in Dearborn, an MS in optics from the University of Rochester, NY, and a PhD in electrical engineering from the University of Illinois at Champagne-Urbana. (Plano can be reached at 408/943-9700 or maryanne.plano@novellus.com.)

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