Analysis and Metrology—Yield Management

Using bitmap analysis to help identify yield-critical issues in the fab

Analytical software that can manipulate data in a variety of ways facilitates the correlation of bitmap failures to specific process steps.

David M. Schraub, Motorola; and Shawn Smith and David Guidry, Knights Technology, a division of Electroglas

In the semiconductor industry, bitmapping has always been a key element in yield enhancement engineers' tool set for determining the root cause of low-yielding materials. Indeed, in the mid- to-late 1980s, memory bitmapping and associated follow-on failure analysis laboratory work were considered the primary techniques for in-fab failure debugging efforts, along with the use of parametric electrical test data. Although a number of in-line defect reduction methods have been introduced since then (for example, in-line scanning electron microscopy and voltage-contrast defect detection tools), performing bitmap failure analysis is still considered critical to the yield ramp.

Many fabs use commercial yield management databases such as YieldManager by Knights Technology (Sunnyvale, CA), which makes it easy to overlay in-line defect inspection data with end-of-line bitmap failure data for analysis. Such advanced software has greatly increased the ability of engineers to analyze bitmap data. Whereas in the past failure analysis involved painstaking visual wafer inspections, interspersed with difficult deprocessing steps, today engineers can tie die failures directly to historical inspection data. Previously, each engineer could analyze only 10 or 20 failures per week, thus providing very limited information. Now engineers can routinely bitmap a sample of wafers from every lot and quickly provide hundreds of data points for analysis.

One facility that uses Knights yield management software is Motorola's MOS-13, an 8-in. wafer fab in Austin, TX. In operation since 1996, this fab produces a variety of chip types, including SRAM and embedded SRAM devices. This article discusses the bitmapping program that was implemented at MOS-13 to assist engineers in identifying yield-critical issues within the fab.

Procedural Challenges

There are many challenges to obtaining useful bitmap data and correlating such data to in-line defect inspection data. Key technical processes that were addressed by the MOS-13 bitmapping program included:

• Logging bitmap failure data in an established file format.

• Translating failure location addresses from electrical x-y coordinates to physical row-and-column coordinates.

• Translating physical row-and-column addresses within the memory array to vectors within the chip.

• Verifying the accuracy of the bitmapping coordinates output from automated test equipment (ATE).

• Determining the offset between bitmap failure data and in-line defect inspection scans.

Each of the these processes and their associated challenges are described in this article, along with the use of software tools for failure and defect correlation analysis. Although the discussion is specific to the MOS-13 fab, the issues covered are similar to those faced by most semiconductor fabs that use bitmap analysis as a yield enhancement tool.

Logging Bitmap Data. Most attempts at using bitmaps for failure analysis of complex embedded memories such as SRAMs require a thorough knowledge of the devices' array built-in self-test (ABIST) output, which is used as the starting point in the bitmapping process. To obtain useful bitmap data, the ABIST output must contain enough information so that all the failed bits within the memory are logged to the ATE data file. If the test program is written without regard to the data's use in failure analysis, the output to this file may contain data only at the pass-or-fail level.

In addition to the need for sufficient ABIST data, it is important that such data be formatted correctly. Test program data that are output in an arbitrary format require special translators before any further analytical work can be done. This translation is a slow and tedious exercise that would need to be performed for every product, causing delays in providing bitmap data for failure analysis efforts. Thus, one of the first challenges addressed at MOS-13 was the establishment of a standard bitmap format for ATE outputs.

Translating Data from Electrical to Physical Addresses. The electrical-coordinate address of a given bit of information about a memory array that is provided by the ABIST output is usually different from the data's intuitive row-and-column address. For example, it could reasonably be assumed that the lower left corner of a memory array is indexed as x = 1 and y = 1, with the x and y variables increasing with the number of bits in the rows or columns. However, this is not the case for electrical coordinates. Thus, it is necessary to translate, or descramble, the electrical coordinates into the intuitive row-and-column addresses for bitmap failure analysis. At MOS-13 this is accomplished for each chip design by using a standard scramble table that indicates how the electrical addresses correspond to row-and-column addresses. The fab's use of a standard ATE bitmap file format coupled with this standard scramble table enables it to reuse bitmap translation programs for subsequent chip designs, saving considerable engineering time and resulting in faster yield learning on new devices.

Translating Row-and-Column Data into Vectors. Bitmap row-and-column addresses must be translated into physical vectors, referenced from the corner of the chip, so that the failure data can be correlated with in-line defect inspection data. Most in-line defect inspection tools use formats locating defects relative to either the absolute center of the wafer or the lower left corner of each scanned die. Consequently, many commercial yield enhancement databases, such as that used at MOS-13, store defect information by defining a defect's location relative to the wafer's center and/or chip grid. In order to overlay the bitmap data with the in-line inspection data, the bitmap data must be converted to a format common to the defect files.

Converting row-and-column bitmap data to physical vectors within the chip is done at MOS-13 using Merlin's Framework K-Bitmap software (also from Knights Technology). This module allows the user to interactively define the relationship between the memory cell locations on the CAD layout and the row-and-column addresses for the cells. The point-and-click setup routine produces a memory specification file for the chip, which is used in conjunction with a user-defined configuration file and translation executables to produce a standard defect format file for use in defect overlay analysis.

This software performs bitmap clustering during the translation process from row-and-column data to physical vectors. The failure categories include single bits, double bits, quad bits, rows, columns, partial rows, and partial columns, among others. Clustering bitmap data into these categories is key to tracing the source of a yield loss to a specific process module. For example, single- or double-bit failures are often caused by a front-end failure mechanism, while multiple-column failures might be caused by a back-end failure mechanism. The software also identifies failure modes that cannot be correlated directly to defects, groups them into a category called noncorrelated, or Judge, and excludes them from later analysis. For example, if a defect in the addressing circuitry caused a block of bits to fail, no defects would be seen in the block itself. Thus, no failure-defect correlation would exist.

Verifying ATE Data Accuracy. Development of an ABIST program is a complicated procedure, often requiring several iterations before the test is qualified as accurate. The ability to compare the location of known defects to test data output is vital to this qualification process. Accordingly, at MOS-13 defects were induced within various blocks within a memory array using a focused ion beam (FIB) tool. Once the defects were induced in known locations within the array, the chip was retested and the translated bitmap output was compared with known faults to determine the precision of the test. In performing such verification testing, multiple faults should be induced in each unique memory block to ensure that the data used for bitmapping is accurate.

Determining the Offset between Bitmap Data and In-Line Defect Data. To analyze the overlay of bitmap data with in-line defect inspection data, the offset between the coordinates of the two data types must be quantified. The vector origin of bitmap data is based on the design at the lower left corner of the chip. The origin point of in-line defect data, which is typically somewhere in the street, or scribe, of the chip, is determined by the yield enhancement engineer when each defect inspection tool recipe is set up. To obtain the maximum overlay capability, all defect inspection recipes should use the same origin point so that a constant offset vector can be applied to the bitmap data.

There are many methods for determining the offset between the two coordinate systems. The one used at MOS-13 involves measuring the distance between archived defect images and the corresponding bitmap failure locations. If these distances are found to be consistent over a sufficient sample, the measurement can be used as the offset vector between the two data types and will yield good analysis results. Another effective method is to scan the damaged die on the FIB-treated wafer that was used for verification testing. By scanning the damaged die with a standard defect inspection tool, classifying the drilled holes with a review code, and then overlaying these defects with their corresponding bitmap failure locations, the overlay offset becomes apparent.

Using Software for Data Analysis

Once the bitmap data have been properly converted and qualified, yield enhancement engineers at MOS-13 use the analytical software to aid in identifying yield-limiting defects within the fab. The software can manipulate data in a variety of different ways and process enough information to ensure meaningful results. The most basic technique used in bitmap overlay analysis is to measure "hits"—that is, instances of electrical bitmap failures that fall within a defined proximity of a defect detected by in-line inspection. The number of hits is typically measured in terms of where within the process flow these overlaps occur and what types of electrical failures they represent.

Figure 1: Defect kill ratios for various inspection steps.

Hit data can be used to calculate a kill ratio for each defect type or at each inspection step. The kill ratio expresses the number of hits from the chosen category (defect type or inspection step) divided by the total number of defect events for that category. Figure 1, for example, shows kill ratios for different in-line inspection steps. A chart such as this is useful for determining the relative yield impact of the defects that appear at various inspection steps. Equipped with relative kill ratio data, yield enhancement engineers can focus limited resources on the process steps at which the most serious electrical faults are detected.

Figure 2: Yield loss by inspection step.

Figure 3: Percentage of die containing hits by bitmap failure category.

Although kill ratios are very effective measures of the deadliness of defects, they do not reflect the actual number of defects present. In some cases, a particular defect type might be rare but deadly, causing a kill ratio of over 90%. Yield loss, a better measure of defects on which engineers should focus, is illustrated in Figure 2. This parameter focuses on die-level results, showing what percentage of die losses are a result of killer defects. Yield loss is calculated by dividing the number of defective die with hits by the number of die inspected. Hit data can also be analyzed and presented in other ways. Figure 3, for example, displays the percentage of die in this investigation that contained hits by bitmap failure category. This type of chart is useful for understanding the percentage of die lost to front-end or back-end failure mechanisms. Table I shows hit and miss information and contains a noncorrelated category referring to failures that cannot be correlated with defects.

Inspection Step	Hit	Miss	Noncorrelated
A	4	122	—
B	—	21	—
C	72	253	—
D	19	280	—
E	12	20	—
F	30	86	—
G	18	15	—
H	2	17	—
I	96	2543	—
J	4	55	—

Table I: Hits, misses, and noncorrelated failures by inspection step. In this case, all failure modes could have been correlated with defects.

Figure 4: Defect hits by inspection step and defect type.

It is important to understand which defect types account for the most hits at each process step. The most straightforward approach is to generate a Pareto chart showing the number of hits versus both defect category and inspection step. A distribution of defect types such as that shown in Figure 4 would provide enough information for process engineers to make changes to control yield-limiting defects. However, because the defect categories are often too broad, it is not obvious which process engineering group must be contacted to eliminate the problem. In such cases, hits must be correlated with images captured by in-line defect inspection tools. The most powerful way to accomplish this is to use a collection of images representing the basic defect categories correlated to the types of electrical failures. Figure 5 shows images of defects classified as hits with electrical bitmap data, along with a modified wafer map showing the bitmap failures. At MOS-13 defect, bitmap, and image data are cross-indexed within the yield management software's database. The software also provides interfaces to load images sent from review tools or from image archival systems, such as those provided by Advanced Database Systems (Boulder, CO) or VARS (San Jose).

Figure 5: A wafer map showing defects and electrical fallout correlation with photos of defects.

Conclusion

The use of bitmapping analytical software to correlate in-line defect fallout to electrical failure and a resulting reduction of cycle time for failure analysis is expected to lead to an overall improvement in product yields at MOS-13. Whereas in the past bitmap analysis required visual inspections, now engineers can tie their failures to historical inspection data supported by in-line photographs.

An interesting result of using bitmapping software in the fab was the discovery that many electrical failures were not being found during in-line inspections because only a 50% scan was being performed. When this rate was increased to 100%, new inspection steps were introduced while others were modified or removed. Therefore, not only is overall yield expected to improve, but the ability of the inspection tools to spot potential problems has also been enhanced.

David M. Schraub has worked at Motorola for four years and is responsible for the administration of YieldManager and Merlin software at MOS-13 (Austin, TX), where he also oversees yield enhancement and failure analysis of the devices produced at the fab. Before joining Motorola, Schraub worked at Advanced Micro Devices and Sony. He is a member of ASM International and the Texas Society for Electron Microscopy. (Schraub can be reached at 512/933-2466 or ra3759@email.sps.mot.com.)

Shawn Smith is a product manager for yield enhancement products at Knights Technology, division of Electroglas (Sunnyvale, CA). He previously served as a yield enhancement engineer at Motorola and a product engineer for Texas Instruments. He received his BS in engineering physics from the University of Oklahoma (Norman) and a master's degree in nuclear engineering from the Bettis (Westinghouse) Atomic Power Laboratory. (Smith can be reached at 512/306-7612 or ssmith@knights.com.)

David Guidry, a product manager at Knights Technology, is responsible for product strategy, roadmaps, and all yield enhancement products. He has been with the division for four years and was the product manager for the first version of YieldManager. Before joining Knights, Guidry worked at Advanced Micro Devices, Philips Semiconductor, and Altera. He holds an MBA from the London Business School and a BS in chemical engineering from the University of California, Berkeley. (Guidry can be reached at 408/522-8909 or dguidry@knights.com.)

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