The 300-mm Imperative

Addressing the 300-mm challenge with new wafer-carrier architecture

Gary Gallagher and Michael Wright, Entegris

The creation of an optimal wafer environment throughout all stages of IC fabrication poses a constant challenge to the semiconductor industry. Regardless of whether this challenge has been felt at the macro level in the cleanroom or at the micro level in a process chamber, the semiconductor industry has evolved because of how it designs wafer environments to keep pace with new contamination control roadmaps.

Methods of wafer transport and storage have also evolved significantly. Early carriers consisted of plastic and foam jewel boxes that carried a single 50-mm wafer, which was handled by tweezers. Wafer-carrier architecture has progressed from these heavy machined and manually handled 100-mm metal cassettes to the much larger 300-mm front opening unified pod (FOUP), which is transported and tracked by means of automated systems. The FOUP is not just another carrier, technical commodity, or big wafer "boat." It is a very sophisticated extension of existing fab equipment that must adhere to exact specifications and be functional, reliable, and dimensionally accurate enough to interface—time and time again—with some of the industry's most precise automation systems.

As part of the effort to develop an optimal system for wafer transport and storage, this article provides guidelines for understanding new carrier architecture, examining 11 critical wafer-environment issues that must be addressed as the semiconductor industry rises to the 300-mm challenge.

SEMI Standardization

In developing next-generation wafer carriers, the IC industry for the first time in its history is codifying international SEMI standards before the implementation of new production techniques. Since the carrier is a pivotal element in the semiconductor fabrication process and it interacts with almost all activities in the fab, its standardization is crucial to industry needs. The evolution of provisional 300-mm standards has prompted changes in existing open cassette and FOUP standards. Difficulties have arisen as the industry has tried to integrate wafer-carrier requirements and standards compliance with innovation and creativity.

The ultimate goal of the user community is to achieve interchangeability and interoperability among suppliers to reduce costs, encourage competition, and lessen the potential for single-point failure. Although this standardization goal has not been fully attained, positive results have been achieved. In the interest of further progress, the International 300-mm Initiative (I300I) plans more studies in the areas of interchangeability and interoperability in conjunction with components suppliers.

Particle Cross-Contamination

Particle cross-contamination caused by wafer storage and transport during the 500 process steps in the fab at 0.13-µm linewidth makes it critical to develop an optimal wafer-carrier environment. International Sematech has published particle per wafer pass (PWP) specifications for 300-mm FOUPs. For 0.18-µm technology, the SIA roadmap has established that the PWP level generated through the transportation, storage, and handling of wafers using FOUPs cannot exceed 0.009 at 0.09 µm. Initial PWP testing conducted by I300I at Sematech indicates that this specification is achievable under controlled conditions. Although the FOUP is an integral part of particle control, the test conditions at Sematech included a complete systems approach to controlling particulation. This system included 300-mm loadports and clean wafer handling within a better than Class 1 minienvironment.

Japan's Semiconductor Leading Edge Technologies (Selete) conducted studies comparing the particle performance of 300-mm open cassettes and FOUPs in Class 1 and Class 1000 environments. Preliminary data suggest that particle performance was well below the target specification of 0.35 PWP at >=0.12 µm. Once again, the wafer carrier was part of a system that included a loadport and a Class 1 minienvironment. Additional particle performance testing is required so that advanced wafer carriers can meet stringent PWP roadmap requirements under normal operating conditions. To better understand performance capabilities, both I300I and Selete plan follow-on studies and will gather data from 300-mm pilot lines utilizing FOUPs.

Airborne Molecular Contamination

Contamination control is essential to minimizing foreign deposits on the wafer surface. While sealing the wafer transport carrier may prevent airborne molecular contamination (AMC) from entering the carrier from the cleanroom, the sealed carrier material may have a tendency to absorb rather than desorb AMC. Ultraclean wafer storage environments may be necessary to protect photoresist-coated semiconductor wafers from AMC, which is thought to result from elevated concentrations of bases, such as the NMP used in photolithography or ammonia and organic amines that exist in cleanroom makeup air or processes. AMC reacts with chemically amplified photoresist to cause image degradation. Traditional wafer cassettes can contain 50 to 100 ppb total base when packaged in contaminated air. Flushing the environment using dynamic airflow through a molecular air filter may maintain AMC concentrations at <5 ppb total base inside the container.

Figure 1: Study of chemical contamination indicates that carbon and boron levels on wafers stored in an open cassette were approximately 10 times greater than those on wafers stored in a sealed FOUP.

Selete performed chemical contamination tests on both the 300-mm open cassette and the FOUP. Two studies compared the effectiveness of open and sealed carriers in resisting carbon/boron and cross-contamination, respectively. Total carbon/boron contamination levels were measured on wafers stored in both types of carriers after one week in a cleanroom. The results, shown in Figure 1, indicate that the contamination levels on wafers stored in the open cassette were approximately 10 times greater than those on wafers stored in the sealed FOUP. Selete also studied cross-contamination levels on wafers stored in a sealed FOUP. Initial contamination levels were measured after wafers had been stored for one month. Then the walls of the FOUP were purposely contaminated with phosphorus and the wafers were stored in it again for one week. Although contamination levels were nearly three times the baseline, they fell again to their initial values after the FOUP was cleaned using a water shower, as illustrated in Figure 2. This demonstrates that some contaminants, once absorbed, can be removed using effective cleaning methods.¹

Figure 2: Study of cross-contamination in a sealed FOUP shows that after the FOUP was contaminated with phosphorus and then cleaned with a water shower, contamination levels fell to their precontamination values.

Using a sonic acoustic wave (SAW) device developed for NASA to measure the real-time submonolayer deposition of contamination, Sematech tests detected low concentration levels of AMC within sealed FOUPs. The SAW's deposition versus time plot is a useful means for measuring the time dependence of the contamination. A thin layer of SiO^₂ on the top surface of the sensor mimics the surface chemistry of an oxidized silicon wafer. Table I presents the SAW deposition-layer data used to calculate the change in AMC frequency over a 10-day period. Using this change, a conversion is made to mass deposition, and the result is used to calculate the thickness of the AMC layer. Because the effect the layer deposition value has on in-process wafers is not well understood, the SAW data are used for comparison only.

Function	Methodology
Change in frequency over 10-day period	202,524 — 202,024.5 = 499.5 Hz
Mass deposition conversion	499.5 Hz x 2 x10—11 g/(cm2 Hz) x 1 ng/10—9 = 9.99 ng/cm3
Thickness-layer conversion (when density of the material deposited is 1 g/cm3	9.99 ng/cm2/1 gm/cm3 = 0.999 Å = 0.099 Å/day

Table I: Sonic acoustic wave data deposition-layer calculation.²Front opening unified pod for transporting and storing 300-mm wafers.

Copper-Related Issues

As feature sizes shrink, more devices can be placed on the die, resulting in decreased gate delays and higher-speed circuits. Increasing density combined with faster devices has expanded the functionality of integrated circuits by a factor of over one billion. However, interconnect conductors have also shrunken and moved closer together, leading to higher line resistance and higher line-to-line capacitance. This poses the problem of slower rather than faster devices.

The development of copper and low-k dielectric (LDE) interconnects addresses the problem of slower devices, offering an increase in performance over aluminum interconnects by a factor of 1.5 to 2, or the opportunity to use finer lines and eliminate one to two metal layers.³ However, LDEs used to dramatically improve chip performance have a high oxidation and corrosion rate. Although ambient humidity levels in cleanrooms are typically controlled at 45% relative humidity, sealing this ambient environment in the carrier with exposed copper may cause the copper to oxidize and corrode.

Methods of controlling the oxygen and humidity levels in sealed carriers have been developed using dynamic inert-gas purge technology. In 200-mm pod applications, sealed carriers are opened and ambient oxygen is flushed out with nitrogen.

In another method, the ambient oxygen environment can be exchanged with nitrogen via filtered inlet and outlet valves while the pod or FOUP remains sealed. During normal operation, the pod or FOUP is sealed from ambient, but when the carrier is docked to the purge station, the inlet and outlet check valves are opened so that the sealed carrier's internal environment can undergo dynamic flush. The dynamic purge method uses a gentle flow of nitrogen on the inlet valve and a complementary vacuum on the outlet valve to control the exchange. This gas exchange must occur as rapidly as possible without turbulence to prevent the deposition of particles on the wafers. Preliminary data demonstrate that this system, using clean dry nitrogen at a flow rate of 4 L/min in a sealed FOUP, can reach levels of 1% oxygen concentration from ambient and 1% RH in less than 6 minutes without adding particles to the wafer.

Although the wafer level effects are not well understood, dynamic purge in advanced wafer carriers may help control organic and inorganic contamination and the oxidation of metals used in semiconductor manufacturing processes during wafer storage and transport.

Precision Automation

The increased use of automation to handle and transport wafers demands that wafer carriers function reliably and precisely. High throughput can be compromised if the wafer carrier is not dependable and consistent, even after multiple uses over a period of years. Advances in wafer-carrier materials, fabrication, and assembly techniques have evolved to improve carrier reliability and dimensional accuracy, facilitating more reliable automation. Historically, open wafer cassettes have had a one-piece injection-molded construction. Advanced 300-mm FOUPs may incorporate dozens of subcomponents requiring complicated assembly and subassembly. In essence, the FOUP has become the newest advanced piece of process equipment in 300-mm fabs.

Suppliers have achieved accurate and consistent assembly by using creative design methods, fixtures, gauges, optical inspection, and in-process quality checks. Random acceptable-quality checks have been replaced by 100% dimensional-quality checks that verify a set of key automation interfaces on every FOUP. Polymer shrink rates and tolerance stackups at assembly are well understood by FOUP suppliers. New techniques to accommodate variations in polymer components have been implemented to provide end-users with advanced wafer carriers that are more precise and consistent from lot to lot.

FOUPs must display structural integrity to accommodate future robust automated material-handling systems. Ceiling-mounted overhead transports (OHTs) might come into use in interbay transfers to lower heavy FOUPs from the transport level onto the equipment loadport. Provisional SEMI standards already specify mechanical interface dimensions for top automation flanges on FOUPs to facilitate overhead transport. OHT suppliers relying on robust and accurate FOUPs will also require precision pickup and placement. The entire automation system will consist of a group of interacting and interrelated components forming a very complex whole. Each component, including the FOUP, must meet stringent performance requirements to deliver satisfactory results.

The transition to 300-mm fabrication has also driven the development of ergonomic technologies such as personal guided vehicles (PGVs), automated guided vehicles (AGVs), rail-guided vehicles, and clean conveyors. These transport mechanisms must have precise, structurally sound interface points so that they can perform reliably with wafer carriers.

Tracking and Logistics

The complexity of the semiconductor process and its numerous steps demand an efficient system of wafer tracking and logistics. Because mistakes in processing phases are unacceptable, anticipatory systems must be implemented. Wafer carriers that address tracking and logistics concerns are in development. Tracking methods include human-readable serialization, machine-readable serialization (bar codes), radio frequencies, and short- or long-range infrared frequencies. End-users can choose one or several different types of tracking options based on their specific needs.

The implementation of many varied processes in the fab, such as CMP, copper, and front- and back-end-of-line steps, has made it necessary to differentiate between wafer carriers used for different processes. Two methods are available in the 300-mm marketplace: a universal color coding system (using transparent red, green, and amber) which visually identifies FOUPs designated for different process steps, and lockout pins on loadports, which prevent the processing of wafers from undesignated FOUPs. Mechanical lockout pins on loadports at defined standard locations prevent undesignated wafer carriers from interfacing with undesignated loadports. Only designated carriers can clear the lockout pins, achieve proper registration, and complete the processing step. This "info pad system" prevents the incorrect processing of wafers.

Hot Wafer Processing

Tool throughput can be increased and cycle times decreased by placing hot wafers into wafer carriers, instead of allowing them to cool to ambient within the process tools. Since advanced wafer-carrier materials such as polyether-ether-ketone (PEEK) are extremely heat resistant, carriers made from these materials can hold hot wafers. Although PEEK's continuous operating temperature is identified as 260°C, wafer-carrier manufacturers do not recommend that hot wafers be placed in PEEK-material carriers at this continuous operating temperature. Data show that outgassing levels increase as the temperature of the polymer material is elevated, which can imperil wafer processing. Because wafer heat limits vary according to different requirements, wafer-carrier suppliers offer a variety of operating temperature specifications.

Front opening unified pod for transporting and storing 300-mm wafers. Photo by Ed Shvartzman.

In sealed wafer carriers such as FOUPs, pressure relief technologies are available to allow hot wafer processing. As wafers cool in a sealed wafer carrier, a vacuum tends to be created. Without pressure release, the vacuum could prevent the removal of a door. To address this issue, some FOUPs have a controlled pressure-release mechanism that operates in combination with a filtered, low-cracking-pressure check valve. This valve is designed to open during the wafer cooldown phase, thus preventing a vacuum.

Static Protection

As features sizes shrink, sensitivity to static increases. Low-humidity environments, oxidation, and corrosion can increase the potential for electrostatic events. Wafer-carrier suppliers rely on new materials such as carbon-filled polymers that reduce static potential. Carbon fillers, in either powder or fiber form, enhance traditional insulative polymers with carbon links, providing a conductive path to ground.

One key to successful static protection during wafer storage and transport is to minimize static potential by having a path to ground via all automation interfaces and carrier registration points on the advanced wafer carrier. FOUP suppliers have addressed this performance issue by constructing wafer supports, top automation flanges, and bottom kinematic coupling plates from carbon-filled materials. Tool and automation suppliers should ground wafer-carrier interfaces to complete the static protection chain.

Wafer Integrity

As wafer diameters increase, wafers become heavier, more fragile, and more prone to sag and warp. Protecting this fragile and expensive cargo is difficult because of the strict
requirements placed on wafer contact areas and other design constraints. Larger wafers supported only at the edges can sag, jeopardizing wafer positional accuracy when the carrier interfaces with the tool. Wafer-support designs up to the 200-mm diameter have sloped angles of approximately 16° from horizontal, allowing the wafer to rest on its edges and prevent bottomside contact. This sloped design permits the wafer to be angled within the pocket. The envelope in which the 200-mm wafer rests can be only ±1 mm from nomimal, severely limiting permitted wafer sag. Since provisional SEMI standards for 300-mm wafers define the wafer envelope as ±0.5 mm from nominal, wafer pocket designs must also be rethought.

The 300-mm wafer has a 0.1- to 0.3-mm center sag when supported in the areas defined by standards. This center sag eats away at the tolerance of the envelope, since FOUP suppliers must accommodate the worst-case center-sag scenario. Some FOUPs position the wafer through bottomside contact within the 3-mm exclusion zone, while others have reduced wafer sloping from 16° to 5°, maintaining edge contact only, yet minimizing the wafer angle in the pocket. However, since engineers suggest that backside contact is unacceptable, wafer handling must conform to the worst-case scenario of a 0.3-mm sag.

Other areas of concern include process-induced warpage and exclusion zones. While theoretical models were originally developed to better understand process-induced warpage, subsequent empirical data from 300-mm pilot lines and process-tool suppliers indicate that process-induced warpage does not occur with FOUPs. Exclusion zones defined in provisional 300-mm SEMI standards for open cassettes and FOUPs are used to develop multiple end-effector designs for wafer handling. These designs are not limited to specifications for transferring 300-mm wafers into high-throughput tools using backside contact with a vacuum, edge grip, or batch transfer. Preliminary feedback and data from research in this field are promising.

Human Factors Engineering

The human element will always be present in semiconductor processing. Thus, the use of larger-diameter wafers sealed in a carrier can present serious ergonomic concerns if the issue is not carefully considered. One problem arises because the sealed carrier's contents must be visible. By manufacturing the wafer-carrier body from transparent materials such as polycarbonate, suppliers can easily rectify this problem. However, studies on clear polycarbonate indicate that this material does not provide filter protection from white light, which is necessary to protect uncured photoresist. Color additives such as red, green, or amber provide necessary protection from white light while allowing fab personnel to view the contents of the FOUP.

Because 300-mm wafers are heavier than their smaller predecessors, ergonomic concerns about stress and repetitive-motion injuries have increased. Handles designed to lift and carry FOUPs manually have both advantages and disadvantages. Although FOUPs have pistol-grip handles that can accommodate different hand sizes, these handles can cause repetitive-motion injuries. To positively address the danger to personnel of fab-related injuries caused by lifting and repetitive motions, standards mandate that all FOUP loadports must be positioned 900 mm above the ground, minimizing the need for technicians to lift and reach. Nevertheless, pistol-grip handles and standard loadport placement heights are not comfortable to all. To deal with the comfort issue, 300-mm open cassettes and FOUPs have multiple automation interface points defined to accommodate PGVs, AGVs, or other types of assisted-lift automation, further minimizing the risk of harm to technicians. In addition, utilizing 13-wafer-capacity FOUPs rather than the larger 25-wafer-capacity models can reduce excess weight concerns.

Shipping

The shipping of 300-mm raw and thinned wafers poses special problems. Traditional boxes for shipping wafers up to 200 mm in diameter consisting of a cassette, base, and cover are being replaced by front-opening shipping boxes (FOSBs) for 300-mm wafers. Based on FOUP technology, FOSBs integrate wafer support and cushioning into two main components: the body and the door. Provisional SEMI standards have been developed so that suppliers can produce compliant products.

The market for thinned wafers and wafer-thinning technologies has outpaced the industry's ability to successfully ship thinned wafers so that they can be easily transported and loaded and unloaded without breakage. Wafer-thinning technologies exist by which a standard 200-mm wafer can be reduced in thickness from 725 to <200 µm. The demand for smart cards, cellular telephones, and other electronic products has given a great boost to the demand for thinned wafers. The need to develop wafer carriers that can ship and handle thinned wafers is driving new designs and future products.

Conclusion

As the semiconductor industry edges into the new millennium, wafer-carrier technology will advance and develop. Wafer management, storage, and shipping will face new challenges. Issues associated with wafer movement are being addressed through creative design, materials selection, and industry standardization. Although questions remain as to how to achieve high yields with feature sizes of <0.1 µm in relaxed cleanroom conditions, it is clear that 300-mm wafers require more advanced handling and contamination control than their smaller forebears. While the evolution from commodity boxes and cassettes to sophisticated FOUPs poses a challenge to the semiconductor industry, an infrastructure of capable suppliers exists to fulfill industry needs.

Acknowledgments

We wish to thank the 300-mm community for the insights they have provided toward the development of this article. In addition, we would like to extend a special thanks to the automation and integration team at SC300 in Dresden, Germany.

References

1. K Tokunaga, AMHS/Minienvironment Section, in Proceedings of the Fourth Selete 300-mm Program Evaluation Process Announcement (Tokyo, Semiconductor Leading Edge Technologies: 1998).

2. International Sematech Technology Transfer No. 98123645A-ENG.

3. K Monnig, "Why Copper and Low K?" Future Fab 5 (1998): 233—240.

Gary Gallagher, director of new business development electronic shipper products at Entegris (Chaska, MN), has worked in the semiconductor industry for more than 15 years in the fields of engineering, project management, program management, people management, product development, marketing, and technical sales. He was the visionary of the new carrier architecture for 300-mm wafers, which has become the predominant carrier choice for 300-mm fabs. Gallagher has published many articles in semiconductor periodicals and has lectured on wafer handling internationally. He holds several international patents. He received his BS in 1981 from the University of Wisconsin (Stout) in industrial technology with a focus on the science of packaging engineering. (Gallagher can be reached at 719/528-2651 or gary_gallagher@empak.com.)

Michael Wright, senior vice president of corporate marketing at Entegris, is a 20-year senior management veteran of the semiconductor and associated industries. He is the founder of Wright Williams and Kelly (WWK), an operational cost-modeling software and consulting firm serving the semiconductor equipment and materials industries. He has published articles in several semiconductor and microelectronics industry publications. A speaker and teacher, Wright has given presentations for IBM, AT&T, and Sematech. He teaches "Understanding and Using Cost of Ownership" and "How to Successfully Manage New Product Introductions" for SEMI. (Wright can be reached at 719/528-2785 or michael_wright@empak.com.)

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