TECHNICAL PROGRAMS
The following list showcases most of the workshops, symposia, conferences, and the like taking place during Semicon West 99 week. The events scheduled for San Francisco are listed first, in chronological order, followed by the San Jose program. For complete information, log onto http://www.semi.org or call SEMI at 650/940-6905.
SAN FRANCISCO
SUNDAY, JULY 11
1—5 p.m.
Workshop on Gas Distribution Systems
S.F. Marriott
Program Chair: Jack Martinez, NIST
Cold Drawn, High-Purity 316L Stainless Steel for Gas Distribution Systems
Michael Antony, Allvac; and Paul Morris, Ormet-Wah Chang
Field Applications of All Vapor-Phase Delivery of Electric Specialty Gases
Hwa-Chi Wang, R. Idischas, G. Rameau, J. Paganessi, and C. Schnepper, Air Liquide
An Analysis of WF6 Installations
Norbert Fanjat, Air Liquide Electronics Europe; Daniel Berenbaum, Applied Materials; and Jean-Marc Girard and Benjamin Jurcik, Air Liquide R&D
Satisfying SEMI S2-93 with a Common String for Both High-Pressure and SDSTM Ion Implanter Sources
Eric Redemann and Patrick Lowery,
Z-BLOC Modular Gas Systems
Gas System Design Requirements
D. Ruppert and S. Farber, BOC Edwards
Compatibility of CO with Various Metals and Metal Alloys Used in Gas Delivery System Components for the Semiconductor Industry
Robin Binder, Steve Mankowsky, and Gregory H. Leggett, Millipore
Using Lower Fluorine Concentration Mixes for Corrosive Gas Delivery System Passivation
Brian Felker, Eugene Karwacki, and Ronald Pearlstein, Air Products and Chemicals
HBr and HCl Delivery from Gas Cylinders and Tube Trailers: Moisture and Metals Analysis
Andrew D. Johnson, Suhas Ketkar, Karen Marhefka, and Richard V. Pearce, Air Products and Chemicals
Ultra-High-Purity Bulk Specialty Gas Package for 300-mm Wafer Fabrication
Robert Torres, Joe Vininski, Erik Henning, Matheson Gas Products
Workshop on Contamination in Liquid Chemical Distribution Systems
S.F. Marriott
Program Chair: John Bare, FSI International
Ultra-High-Purity Sampling System for Noninvasive Sampling at Point of Use
Samantha Tan, Jennifer Le, James Mackenthun, and Vaughan Salson, ChemTrace
Comparison of Optical Particle Sensors Used to Measure Particle Concentration in High-Purity Chemicals
Debra Carrieri, FSI; and Donald C. Grant and Wayne Kelly, CT Associates
Preserving CMP Slurry Health through Proper Handling and Preventive Maintenance
John Barre, FSI; Stan Lesiak, Cabot; Rob Rhodes, Rodel; Jeff Wilmer, MEGA Systems and Chemicals
Particles in Bulk Chemical Distribution Systems with an Internal Circulation Loop
Mindi Zu and Kevin Chang, Air Liquide Chicago Research Center; and Herve Dulphy, Blaise Hovine, and Pascal Moine, Air Liquide
Status of Industry Standards for Liquid Chemical Distribution Systems
Dianne Dougherty, ChemTrace
Advancement in the Rapid Detection of TOC in High-Purity Water Sytems
Anthony C. Bevilacqua, Thornton Associates
New Instrumentation for Accurate, Low-Level TOC Measurement
Karen Franklin, Slava Petropavlovskikh, and Kent Stephens, Sievers Instruments
MONDAY, JULY 12
8 a.m.—noon
Design Practices for Higher Equipment Reliability (tutorial)
Argent Hotel
Instructor: Vallabh Dhudshia,
Texas Instruments
STEP: SEMI E78-0998 Electrostatic Compatibility of Equipment
S.F. Marriott
Program Chair: Arnold Steinman, Ion Systems, ESD/ESC task force leader, SEMI International Standards Program
Introduction: The Basics: Static Charge Problems, Electrostatics, Measurement Techniques and Static Control Methods
Arnold Steinman, Ion Systems
Types and Measurements of ESD Damage to Components
Leo G. Henry, Oryx Instruments
Minimizing Electrostatic Attraction of Contamination
Robert Donovan, Sandia National Laboratories
ESD Effects on Front-End Equipment
Julian Montoya, Intel
ESD Effects in Test and Assembly
Wayne Tan, Advanced Micro Devices
Implementing SEMI E78-0998, User/Manufacturer Collaboration to Achieve the Static Levels in the Guide
Arnold Steinman, Ion Systems
8 a.m.—5 p.m.
Silicon Wafer Symposium
S.F. Marriott
Program Chairs: SooKap Hahn, Pacrim Technology; and Tohru Hara, Hosei University
Current Status of Starting Materials Requirements for the 1999 International Technology Roadmap for Semiconductors (ITRS)
Howard Huff, Sematech
Novel Wafer Technologies for 130 nm and Below
P. K. Vasudev, National Instruments
The Wafer Quality-Price Dilemma -- What Do We Do About It?
K. V. Ravi, Intel
Challenges of Material Properties for Advanced DRAM Devices
J. G. Park, Samsung Electronics
Advances in the Defect Engineering of Polished Silicon Wafers: Perfect Silicon and Magic Denuded Zones
Robert Falster, MEMC
Point Defect Controlled CZ Silicon Crystal Growth for ULSI Device Applications
George Kim, LG Siltron and KMK Associates
300 mm — Why, When, and What
Ron Horwath, Cap Gemini-America
Challenges and Opportunities in 300-mm Si Wafer Preparation
Hermann Fusstetter, Wacker Siltronic
Epi-Optimized Substrates (EOS) -- Epi Quality and Performance at Costs Below Advanced CMP Polished Wafers
Malcolm Russ, MJR Technology Management
Advantages and Issues of Silicon Epitaxial Wafers for Advanced Devices
Hidekazu Yamamoto, Mitsubishi Electric
Current Status and Future Challenges in Large-Diameter Si Epitaxial Reactor Technology
Norma Riley, Applied Materials
Is Silicon-Germanium Technology Oversold or Underexploited? An Overview of Production Epitaxial Techniques, Current Status, and
Market Potential
Derek C. Houghton, SiGe Microsystems
SOI for Mainstream CMOS: Challenges and Opportunities
G. Shahidi, IBM
SOI Materials and Process Technology : Status and Issues for Mainstream Insertion
M. Mendicino, Motorola
Analog Application and Wafer Reliability of SOI Materials
Makoto Yoshimi, Toshiba
Genesis Process for Cost-Effective SOI Substrate Manufacturing
Igor Malik, SiGen
Symposium on Contamination-Free Manufacturing (CFM) for Semiconductor Processing
S.F. Marriott
Program Chairs: Sowmya Krishnan,
Ultra Clean Technology; and Ahmed A. Busnaina, Clarkson University
Critical Requirements for Very-High-Quality Processes in 300-mm Production
Tadahiro Ohmi, Tohoku University
Particle Defect Reduction in the Endura Titanium Nitride PVD System
Mark Louis, Diane Peebles, and
Roger Spencer, Sematech
Understanding the Behavior and Impact of Trace Contaminants in High-Purity Plasma Process Gases
A. C. Allgood, Zyron Electronics Gas, DuPont Fluoroproducts
Deep-UV Laser Removal of Organic Surface Contamination from Semiconductor Surfaces
D. Elliot, UVTech Systems; and V. Houlding, Matheson Gas Products
Improved Oxide Etch Repeatability through In Situ Monitoring and Advanced Process Control
Kurt Christenson, FSI
Solvent-Free, Dry, Postetch Cleaning for
the Advanced Interconnect
Andrew Kirkpatrick, GaSonics
Poster Session, featuring papers from Applied Materials, Ultra Clean Technology, IBM, Pall Corporation, VLSI Technology, BOC Edwards, MicroTherm, Clarkson University, TSMC, Sumitomo Heavy Industries, Japan Analytical Corp., University of Minnesota
Determination of Parts-Per-Trillion Levels of Transition Metals in
an SC-2 Bath
Beverly Newton, Dionex
Precision Cleaning of Semiconductor Surfaces Using Supercritical Fluids
J. B. Rubin and L. Dale Sivils, Los Alamos National Laboratory; and A.A. Busnaina, Clarkson University
CMP Defectivity and the Impact on Manufacturability of CMP Process Flows
John Givens, VLSI Technology
New One-Pass SC-1 Cleaning Process
R. M. Hall, Elizabeth Hansen, Josh Butler, and Tamer Elsawy, SCP Global
Study of Gate-Oxide Breakdown Influenced by RCA Clean
H. H. Chang, J. J. Chang, C. D. Chang,
W. J. Liou, and Y. J. You, TSMC
8:30 a.m.—5:30 p.m.
Lithography Challenges and Opportunities
S.F. Marriott
Program Chair: Lars Liebmann, IBM Microelectronics
Introduction and Overview: The SIA Lithography Roadmap
Lars Liebmann, IBM Microelectronics
Deep-UV Optical Lithography
Harry Levinson, Advanced Micro Devices
Extreme-UV Optical Lithography
Chuck Gwyn, Intel
SCALPEL E-Beam Projection
Alex Liddle, Lucent Technologies
PREVAIL E-Beam Projection
Hans Pfeiffer, IBM Microelectronics
Panel Discussion
Chemical Vapor Deposition (CVD) for Integrated Circuits (tutorial)
Argent Hotel
Instructor: Ted Kamins, Hewlett-Packard Laboratories
Environmental Impact of Process Tools (presented in cooperation with SIA)
S.F. Marriott
Program Cochairs: Larry Zazzera, 3M; Jerry Meyers, Intel; and Peter Maroulis, Air Products and Chemicals
Opening Remarks
An Environmental Design Tool for Semiconductor Process Tools
Sara Thurwachter, Jerry Schoening, and Paul Sheng, Applied Materials
PFC Emissions Reduction through Remote Plasma Cleaning for Applied Materials Dielectric CVD Chambers
Laura Mendicino, Motorola; and Alan Atherton, Applied Materials
Reduced Emission Chamber Clean Processes on Novellus CVD Chambers
Kenneth Aitchison, Novellus
Real-Time, Low-Concentration Monitoring of Tool Effluent Compounds Using Optical Techniques
Curtis Laush, Radian International
Online F2 Analysis Using a Novel Extractive FTIR Technique
S. Kesari, W. Reagen, D. Fall, and L. Zazzera, 3M
Empirical Modeling of Emissions from an Oxide Etch Process
R. G. Ridgeway, Air Products and Chemicals; and Graham Hills, Lam Research
Lowering Environmental Impact of Centrifugal Acid Spray Processors
Erik Olson, FSI
Wafer Cleaning Using an Environment-Friendly Argon/Nitrogen Cryogenic Aerosol Process
Natraj Narayanswami, James Weygand, and Kurt Christenson, FSI
Copper CMP Effluent Treatment via Ion Exchange
Laura Mendicino, Motorola; and Phil Kemp, USFilter
SiH4-Based CVD Process Abatement Using a Wet Scrubber
Josep Arno, ATMI-EcoSys
FTIR Measurements of a Silicon Etch Process: A Quantitative Method to Determine Emission By-Products
Jerry White, Carl D'Acosta, and Jerry Cripe, Motorola
VOC Emission Measurement and Reduction for an IPA-Based Semiconductor Wafer Dryer
Andrew Luedtke, SCP Global Technologies
Performance, Cost, and Water Use Gains in Immersion Wet Tools
Ron Chiarello, Stanford University; and Russ Parker, Hewlett-Packard
9 a.m.—5 p.m.
Software Inspections
Argent Hotel
Instructors: Dwayne Knirk and Patricia A. Trellue, Sandia National Laboratories
Understanding and Using Cost
Of Ownership
Argent Hotel
Instructors: Wright Williams
& Kelly
1—4 p.m.
Stainless Steel and Surface Analysis Standards Workshop
S.F. Marriott
Presented by Ron Hendry, Parker Hannifin, Parker UHP Products Division, Facilities and Safety Division Cochair; and Tim Volin, Parker ICD, Surface Analysis Task Force Cochair
1—5 p.m.
Low-K Dielectric Materials Technology Conference
S.F. Marriott
Program Chair: Victor Ku, VLSI Technology
Low-K Dielectric Materials for Advanced Interconnects: Material Properties, Integration and Packaging Issues
Andrew McKerrow, TI; and Carlye Case, Bell Labs
Low-K Materials for IC Intermetal Dielectric Applications: An Updated Status Report on the Leading Candidates
Neil Hendricks, AlliedSignal Electronic Materials
Low-Dielectric Constant Materials for Interlayer Dielectrics in ULSI Devices
Chuanbin Pan, J. Leu, S. Fang, and C. Chiang, Intel
Etch Process Development for Low-K Dual Damascene Structures
Graham Hills, Lam Research
PECVD Prepared Low-K Films
Alfred Grill, IBM Microelectronics
Black Diamond CVD Low-K for Damascene
David Cheung, Applied Materials
STEP: Semiconductor Manufacturing Equipment Voltage Sag Immunity
S.F. Marriott
Program Chair: Michele Negley, Salt River Project
TUESDAY, JULY 13
8 a.m.—noon
Copper Interconnect Status
S.F. Marriott
Program Chair: Mazhar Hussain, Sematech
Copper Interconnect Roadmap
Bob Havemann, Sematech
Reliability of Copper Metallization for ULSI Applications
H. S. Rathore and D. B. Nguyen, IBM Microelectronics
PVD/CVD Barrier and Seed Layers for Copper for sub-0.18 µm
K. Ashtiani, M. Biberger,
C. D'Couto, M. Danek,
E. Klawuhn, K. Levy, and
D. Smith, Novellus Systems
Materials Integration Issues for Low-Dielectric Constant Materials and Copper Metallization
Robert J. Fox, Motorola
Integration and Electrical Performance of Copper Low-K Dielectric Dual Damascene
Dennis Yost, Applied Materials
Cluster Tool Metallization for Copper-Based ULSI Interconnects
Ajit Paranjpe, Lino Velo, Tom Omstead, and Mehrdad Moslehi, CVC
Enabling Metal Deposition Technologies for Advanced Copper Interconnects
Shu Jin, Intel
8 a.m.—5 p.m.
CMP Technology for ULSI Interconnection
S.F. Marriott
Program Chairs: SooKap Hahn, Pacrim Technology; Wilbur Krusell, Lam Research; and Kathleen A. Perry, Obsidian
Integration of Copper Damascene Metallization
T. Cacouris and Eliot Broadbent, Novellus Systems
Gap-Filling Electrochemical Deposition Process for Cu Damascene Process
Chiu Ting, CuTek Research
Technoeconomic Aspects of Integrated CVD-CVD Copper Interconnect
Ahmad Kermani, CVC
Properties of Cu Films Deposited by Ion Plating Method
Toshio Kudo, Sumitomo Heavy Industries
Chemical-Mechanical Planarization for Integrated Circuit Manufacturing
Wei-Tsu Tseng, National Cheng-Kung University
Maintaining Polish Productivity in Spite of CMP Consumables Variability
Christopher H. Raeder, AMD
CMP of Copper Damascene Structures at Sematech
Steve Hymes, Sematech
Characterization of Pattern-Dependent Variations in Copper CMP
Tae H. Park, MIT
Cu CMP Cleaning
John de Larios, OnTrak Systems
The Effects of Thickness on Resistivity of Metal Films in the CMP Process
Walter Johnson, KLA-Tencor
Progress in Metal CMP
Michael Oliver, Rodel
Filtration of CMP Slurries: Filter Selection, Implementation, and Filter Life Optimization
Zhenwu Lin and Geanne Vasilopoulos, Millipore
Design Features and Considerations of Cu CMP Slurries
Katsuyoshi Ina, Fujimi
CMP Wastewater Treatment
Michael Hahn and Steve Allen, Microbar
Metal CMP: Cu Polish, Cleaning and Contamination Control
Manabu Tsujimura, Ebara
Multiple CMP Process Approaches to and Issues with Cu Dual Damascene Planarization on a Multitable Tool
John Boyd, Brian Pautsch, Hirouki Maeda, and Randy Johnson, Strasbaugh
A Two-Step Copper CMP Process Using Two Slurries on a Multihead
S. Basak, T. Laursen, T. Murrella, and Malcolm Grief, SpeedFam-IPEC
Development of Intelligent CMP
Yamato Samitsu, Kazuo Kobayashi, and Eiichi Yamamoto, Okamoto Tool Works
9 a.m.—5 p.m.
Software Testing
Argent Hotel
Instructors: Dwayne Knirk and Patricia A. Trellue, Sandia National Laboratories
Overall Equipment Effectiveness: Improving Equipment Productivity
Argent Hotel
Instructors: Doron Meyersdorf, Tefen; and John Fowler, Arizona State University
10 a.m.—noon
SEMI Chemical and Gas Manufacturers Group (CGMG)
S.F. Marriott
1—5 p.m.
Resolution Enhancement Technologies in Optical Lithography (tutorial)
(also, July 14, 8 a.m.—NOON)
S.F. Marriott
Instructor: Lars Liebmann, IBM Microelectronics
Wafer Fab Design: Current and Future Challenges
S.F. Marriott
Program chairs: Doron Meyersdorf and Amnon Raviv, Tefen
Architectural, HVAC, and Mechanical Issues in 200/300-mm Fab Design
Michael Uyeda, Graeber, Simmons & Cowan; and Thane Joyce,
Lockwood Greene
Fab Automation and Integration Trends
Ray Martin, Asyst
Factory Logistics and Interbay/Intrabay Material Handling Systems
Theron Colvin, PRI Automation
Tool Layout in 300-mm Facilities
Doron Meyersdorf and Amnon Raviv, Tefen
Modular Fab Design
Lindsey Leveen, Bechtel
VR Modeling for Fab Design
Coby Everdell, Bechtel
3—6 p.m.
EHS Interest Group Meeting
S.F. Marriott
WEDNESDAY, JULY 14
8 a.m.—noon
CIM Framework: Creating an Integrated Fab Solution from the Shop Floor to
the Enterprise
S.F. Marriott
MES Integration with Cell Control
Kurt Milne, Camstar
Standardizing on Windows NT: An Integrator's Perspective
David Hamu, TRW
ERP Systems
David Busch, Oracle
Cell Control
Ashish Chona, Asyst Technologies
MES Integration with ERP
Douglas Scott, Promis Systems
STEP: The Sensor Bus Advantage
S.F. Marriott
Program Chair: Dale Blackwell, International Sematech
8 a.m.—3 p.m.
Flat Panel Display Manufacturing Technology Conference
S.F. Marriott
Program Chair: Bill Lee, Symmorphix
8:30 a.m.—3:30 p.m.
Semiconductor Industry/Education Partnerships: Shaping a New Workforce for the 21st Century (cosponsored by SEMI, SIA, and Joint Venture: Silicon Valley Semiconductor Industry Education Partnership)
W Hotel, San Francisco
Industry and education participants, at publication date: Applied Materials, Harris Semiconductor, Hewlett-Packard, Infrastructure, Intel, KLA-Tencor, Komag, LSI Logic, Lucent Technologies, National Semiconductor, Schlumberger, Silicon Valley Group, Spectrum Technologies, Ultra Clean Technology, Ultratech Stepper, Xandex, DeAnza College, DeVry Institute of Technology, East Side Union High School District, Gavilan College, Mission College, Ohlone College, San Jose/Evergreen Community College District, San Jose State University, Santa Clara County School District, Santa Clara University, University of California
1—5 p.m.
MEMS Manufacturing Challenges: Producers Discuss Future Equipment and
Materials Needs
S.F. Marriott
Program Chairs: Steven T. Walsh, Anderson School of Management, University of New Mexico; Glen Dahlbacka, Lawrence Berkeley Laboratories; Sid Marshall, Micromachine Devices
Challenges in Modeling, Designing and Manufacturing MEMS Products
Vladimir Vaganoz, EG&G IC Sensors
MEMS Manufacturing Gotchas
Karen Marcus, Cronos
Commercialization of LIGA Intellectual Property
Jill Hruby, Sandia National Laboratories
MEMS Markets and Opportunities
r Grace, Roger Grace Associates
Expanding HARM-Based Manufacturing Opportunities
Job Elders, TMP
New Opportunities in Bonded Wafer Technologies for MEMS
Kenneth Farmer, NJIT MEMS Center
MEMS Manufacturing Strategies
Bill Higdon, Hewlett-Packard
CMP and Sacrificial Surface Micromachining
Jim Smith, Sandia National Laboratories
8:30—11:30 a.m.
SEMI Market Briefing: Equipment and Materials Market Briefing
Moscone Center
Semiconductor Market Outlook and Trends
Fred Zieber, Pathfinder Research
Semiconductor Equipment Market Outlook and Trends
John Schuler, SEMI
Semiconductor Materials Market Outlook and Trends
Elizabeth Schumann, SEMI
SAN JOSE
TUESDAY, JULY 13
8:30 a.m.—5:30 p.m.
Advanced Packaging Technologies (tutorial)
(also July 14, same time)
S.J. Hilton and Towers
Instructor: Charles Bauer, TechLead
Second Annual Semiconductor Packaging Technologies Symposium
(see also Sessions 5—8 on July 14)
S.J. Hilton and Towers
Keynote Speaker: Bert Haskell, vp of commercial electronics technology, Microelectronics and Computer Technology Corp. (MCC)
Session 1: New Developments in Fine Pitch Interconnect
Session Chair: Raj Pendse, Hewlett-Packard
Ultrafine Pitch Wire Bonding: Fine Tuning Material, Bonding Tool, and Wire Bonder Interrelationships for Optimum Process Capability
Lee Levine, K&S Packaging Materials
50-µm Ultrafine Pitch Ball Bonding under Full Manufacturing Environment
Souad Arsalane, ESEC; and Michael Garnier, STMicroelectronics
Manufacturability of 60-µm Inline and 40-µm Staggered Wire Bond Packages
Mark Eshelman, Kulicke and Soffa Industries; and Willmar Subido, Texas Instruments
Reliability Evaluation of Laminate Multilayer Ultrafine Pitch Wire Bond Modules
Thomas R. Homa, IBM
Process Control in Laser Welding of Electronics
M. Schmidt and M. Geiger, Lehrstuhl für Fertigungstechnologie
High-Density Package Applications for Wire Bond and Flip Chip: Small, Fine Pitch BGA Packages
Mark J. Kuzawinski, IBM
Session 2: Chip Scale Packaging Assembly
Session Chair: Vern Solberg, Tessera
High-Volume CSP Assembly of DRAM and SRAM Devices
Robert Peeter, Alphasem
The BCC++CSP: RF Packaging for Cellular Phones--Miniaturization to the Extreme
Michelle Hou, Fujitsu
Development of Silicone Encapsulants for Chip Scale Packaging
Ann W. Norris, Stanton J. Dent, and Edward J. Benson, Dow Corning
Void-Free, Flux-Free Process for Placement and Attach of Solder Balls to Wafers, Flip Chips, CSP and BGA Packages
Richard Ramos, Scientific Sealing Technology
Advances in Encapsulation and Singulation Enable Matrix Land Array Production
Vada W. Dean, Towa America
Burn-in Sockets for Memory CSP's--A Design and Development Process
James Forster and Peter Taxidis, Texas Instruments
Session 3: Wafer-Level Packaging
Session Chair: Tom Chung, Aptos
Wafer-Level Packaging Technology: A Fad or Terminator?
Tom Chung and Ian Yee, Aptos
Technological Issues Driving Wafer-Level Packaging
Thomas DiStefano, Tessera
The Process Development of Integrated Sensor Wafer-Level Using Thick Film Sealing Glass
DaXue Xu and Henry Hughes, Motorola
Wafer-Level Packaging for Low-Cost, Low-Lead-Count Devices
James Young and Howard Clearfield, Intarsia
Wafer-Level CSP for Analog Applications
Luu Nguyen and Ranjan Matthew, National Semiconductor
Compliant Wafer-Level Package (CWLP)
Chirag Patel, Kevin P. Martin, and James D. Meindl, Georgia Institute of Technology
Wafer-Level Burn-In and Test
Mark Carbone, Aehr Test Systems
XBGA--A Wafer-Level Packaging Process for Chip-Scaled Devices
Anna Lee, Xicor
Session 4: Material Challenges in Packaging
Session Chair: Guna Selvaduray, San Jose State University
Printable Silicone Die Attach Adhesives and Spacers
Ann Norris, Michael Watson, and Steve Wilson, Dow Corning
A Thermoplastic Encapsulant for Electronic Packaging II
Paul Koning, Amoco Electronic Materials
Temperature Effects on Encapsulant Dispensing
Alan Lewis, Christian Ness, Horatio Quinones, and James Carbin, Asymtek
Wire Bonding Optimization for Palladium-Plated Leadframes
Anand Shukla, Kulicke & Soffa Industries
Microstructural Characterization of Au Wire Bonds to Copper Substrates
Rajat Batra, Arjan Auto; Nikhil M. Murdeshwar, Kulicke & Soffa Industries; and William Baeslack III and Kevin Ely
The Measurement of Thickness and Composition in Lead (Pb)-free Solder Plating
Keiichi Sugihara, Seiko Instruments
Enabling Grid Array Modules through Advanced PWB Surface Finish
Chap Haddon, John Konrad, James Stack, Roy Magnuson, Dan Massey, and Mark Plucinski, IBM Microelectronics
New Possibilities Realization: Thick-Film Intelligent Multienzyme Biosensors for Medical Applications
Stanislaw Hodorowicz, Jagiellonian University
WEDNESDAY, JULY 14
8:30 a.m.—5 p.m.
Second Annual Semiconductor Packaging Technologies Symposium (continued from July 13)
S.J. Hilton and Towers
Session 5: Flip Chip Interconnect
Session Chair: Luu Nguyen, National Semiconductor
Hydrogen Fluxless Soldering of Flip-Chip Solder Joints
C. Christine Dong, Air Products and Chemicals
Investigations on Fluxless Flip Chip and Chip-on-Substrate Assembly Using Solder Joints under Different Atmospheres in a Vacuum/Overpressure Solder Reflow Oven
C. Kallmayer, R. Tschernev, R. Aschenbrenner, and H. Reichl, Fraunhofer Institute for Reliability and Microintegration
Flip Chip Underfill Process Guidelines and Considerations
Brent Bacher, Dexter; and Galen Kirkpatrick, ABPAC
Underfill Flow Considerations Using Molecular Dynamics and Discrete Element Modeling
Nancy Iwamoto, Johnson Matthey Electronics; and M. Nakagawa, Colorado School of Mines, Dept. of Engineering, Particulate Sciences and Technology Group
Process Assembly Development for High-Density ASIC Flip Chip/Plastic Ball Grid Array Packages
Mohamed Belazzouz, Miguel A. Jimarez, Eric Duchesne, Luc Ouellet, Francois Guindon, Son Tran, and Glenn Dearing, IBM
Mechanical Reliability Analysis of an Electroplated Bumped Die Flip Chip BGA Package
Armando Carrasco and Trent Thompson, Motorola
Enhanced Ceramic Column Grid Array Technology for High-Performance Flip Chip Carriers
S. K. Ray, M. Cole, L. Achard, I. DeSousa, G. Martin, M. Interrante, and C. Reynolds, IBM
Session 6: High-Density Interconnect Substrates
Session Chair: Vivek Dutta, Johnson Matthey Electronics
Advanced Laminate for High-Density Interconnect Substrates
Gordon Smith, Nancy Androff, Jeffrey Gotro, and Brian Bedwell, AlliedSignal Electronic Materials; Richard Clancy and Ellis Craddock, AlliedSignal Substrate Technologies and Interconnects
High Density Build-Up (HDBU) Technology
Shigeru Ohwada, Hidetoshi Yugawa, Satoshi Yoshiura, Masaaki Harazono, Masaaki Hori, and Katsura Hayashi, Kyocera Japan
Optimal Printed Wiring Board Design for High I/O Density Chip Size Packages
Chirag Patel and James D. Meindl, Georgia Institute of Technology
Bottom-Side Thin Film Structure on the High-Density MCMs Used in S-390 G5 Mainframe Systems
A. K. Molhotra, D. C. McHerron, B. Ghosal, D. Scheider, G. Martin, R. Sheilds, and J. R. Pennachia, IBM
Substrate Plating Factors Necessary for High-Quality Wire Bonding on BGA
Mark Eshelman and Daniel T. Brown, Kulicke & Soffa Industries; Ron Huemoeller and Frank Cordes, Amkor Technology
A High-Performance, Low-Stress Organic Laminate Flip-Chip BGA Carrier
Dave J. Alcoe, Thomas E. Kindl, James P. Libous, Cheryl L. Tytran-Palomaki, John S. Kresge, and Randall J. Stutzman, IBM
Session 7: Advanced Packaging Applications, Markets and Trends
Session Chair: Chung Ho, MicroModule Systems
Future Trends in CSP: New Developments and High-Volume Applications
Jan Vardaman, TechSearch International
Array Packages in Real World Systems
Charles Lassen, Prismark
Chip Scale Packaging for High-Speed RDRAM Memory Applications
Nader Gamini, Rambus
Innovative Chip Mounting Methods on Inexpensive Flexible Antenna Films for RF Smart Cards
Horst Kober, Freudenberg Forschungsdienste
Development of Microwave Multichip Modules for Phased-Array Radar
Yan Wei, Wang Tingyue, Yu Shenlin,
Xie Lianzhong, and Li Xiaoxuan,
Nanjing Reasearch Institute of Electronic Technology
Card Assembly Process Implementation of 1-mm Pitch CCGA
Marie Cole, Phil Isaacs, and Cindy Milkovich, IBM
High-Frequency Electrical Characterization of Glass Ceramic BGA Intended for Wired and Wireless Applications
Edward R. Pillai, IBM
Session 8: Reliability
Session Chair: Atila Mertol, LSI Logic
Thermal and Electrical Characterization of mini-BGA and CSP Packages
Dawit Solomon, Elmer Del Rosario, and Ernie Opiniano, Hana Technologies
Thermal and Electrical Characterization and Design Optimization of QFP Packages
B. G. Guruprasad, Nirmal Sharma, Rahamat Biddin, and Isobel Tan, ST Assembly Test Services
Extending Flip Chip Ball Grid Array Field Life
Charles G. Woychik, David L. Hawken, James. R. Wilcox, and Peter J. Brofman, IBM
CBGA Fatigue Life Improvement
Marie Cole, Greg Martin, Peter Brofman, and Lewis Goldmann, IBM
Controlling Warpage in BGA Packages
David W. Garrett, Amoco Electronic Materials
Achieving JEDEC Level 1 Performance in Encapsulated IC Packages by Understanding the Material Interfaces
Nirmal Sharma, Francis Poh, and Rahamat Bidin, ST Assembly Test Services
Acceptability Metrics for E-Ni/I-Au Metal Finish
Pat Johnson and Matt Kaufmann, Hewlett-Packard
Dry-Pack and Demoisturizing Process Improvements--Breaking the Bakeout Bottleneck
Charles S. Leech Jr., Altos Engineering; and David L. Smith, Level One Communication
THURSDAY, JULY 15
8 a.m.—5 p.m.
IC Trends, Packaging and Testing Issues--An Introduction for
Test Engineers (tutorial)
S.J. Fairmont Hotel
Instructor: Eugene Hnatek, Compaq Computers Tandem Divison
International Packaging Strategy Symposium
S.J. Hilton and Towers
Program Chairs: Charles Bauer, TechLead; and Randy Braun, Johnson Matthey Electronics
Worldwide IC Packaging Markets and Trends
Sandra Winkler, Electronics Trend Publications
Interpreting International Packaging Technology Roadmaps
Michael Pecht, University of Maryland
A Roadmap and Business Strategy of Microelectronics Packaging in Taiwan
Shen-Li Fu, I-Shou University
Technology Roadmap Interactions: Packaging, Interconnection, and Assembly
Happy Holden, TechLead
IBM Chip Packaging Roadmap
Eric H. Laine, IBM
Ceramic Packaging Tradeoffs vs. Plastic Packaging: An Economic and Technology Overview
Bob Lanzone, Kyocera
Equipment Trends and Implications in the Electronics Industry
Ken Cavallaro, Riverview Partners
Impact of Compliant Wafer-Level Packaging into the Next Millennium
Kevin P. Martin, Chirag S. Patel, Paul Kohl, Satoshi Ogitani, and James D. Meindl, Georgia Institute of Technology
New Perspective on Wafer-Level Packaging and Test
James Healy, FormFactor
Production Experiences in Wafer-Level Packaging
Shlomo Oren, Shellcase
Packaging R&D Activities in Taiwan
Enboa Wu, Electronics Research and Service Organization, Industrial Technology Research Institute
Flip Chip from an EMS Perspective
Kim Hyland, Solectron
8:30 a.m.—12:30 p.m.
Eighth Annual Manufacturing Test Conference
S.J. Hilton and Towers
Program Chairs: Paul Emmett, ChipPAC; and Bob Durstenfeld, Hewlett-Packard
Keynote Address—The Coming of Age of Test
Ned Barnholt, executive vp and gm, Hewlett-Packard Measurement Organization
Wafer-Sort vs. Package-Test Strategies: The Future of Package Test
Mark Ojeda, AMD; and Tammy Pelissier, TSK
Package Test: Still the Answer for Low Test Cost
Gary Fleeman, Advantest
Integrating Your Test Cell: Defining, Designing, Developing and Delivering Integrated Work Cells
Bob McIvor, Hewlett-Packard
Work Cell Technology
Andrei Berrar, Credence
The Impact of Strip vs. Singulated Testing: Handling the Small Stuff
Dennis Nelson, MCT
Breaking the Assembly-Test Barrier
Tim Olson, FICO
1—5 p.m.
Test, Assembly and Packaging (TAP) Vision Conference
(cosponsored with the Automated Imaging Assn.)
S.J. Hilton and Towers
Program Chair: Jeff Burnstein, Automated Imaging Association
Vision and Auto ID Applications in Test, Assembly, and Packaging
John Agapakis, RVSI Acuity CiMatrix Fundamentals of Wafer Identification
Mike Kelley, Electro Scientific Industries
Using Machine Vision to Improve Yield in the Die Bonding Process
Jeff Woolstenhulme, Cognex
New 3-D Technology Provides High-Speed, Accurate, and Flexible Coplanarity Inspection
Arye Malek, PPT Vision
The Influence of High-Resolution Vision Systems on Production Yield
Alaert Reinhilde, Siemens Semiconductor
Roll-to-Roll Flexible Circuit Inspection--Identifying and Overcoming the Challenges
David Hoover, Focus Automation Systems
FRIDAY, JULY 16
8:30 a.m.—5 p.m.
Flip Chip Technologies (tutorial)
S.J. Fairmont Hotel
Instructor: Elke Zakel, Pac Tech
(Program information was correct at press time.)
SAN FRANCISCO EXHIBIT HALL HOURS
Monday, July 12
10 a.m.—6 p.m.
Tuesday, July 13
10 a.m.—6 p.m.
Wednesday, July 14
10 a.m.—4 p.m.
SAN JOSE EXHIBIT HALL HOURS
Wednesday, July 14
10 a.m.—6 p.m.
Thursday, July 15
10 a.m.—6 p.m.
Friday, July 16
10 a.m.—4 p.m.
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© 2007 Tom Cheyney
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