INDUSTRY NEWS

1999 ITRS

Roadmap node debate has limited impact on defect reduction work

The five-region committee putting together the 1999 International Technology Roadmap for Semiconductors (ITRS) will most likely reveal its decision on node timing at the July international roadmap conference in Santa Clara, CA. The 1998 revision of the full 1997 document moved several technology milestones ahead by one year, a concession primarily to the rapid pace of process shrinks. For the 1999 ITRS, however, industry leaders are almost certain to return to the three-year cycles that have been used in the roadmap since it first appeared in 1994.

"I think what basically everybody essentially agrees on right now is that in the long term they only feel comfortable with it going back to three years. It's really only a question of what happens over the next couple of technology nodes," says Bob Doering, a senior fellow at Texas Instruments and one of the two North American chairmen on the 10-member International Roadmap Committee. " 'What happens in the next five years?' is the question. Do we have just one more two-year gap between the nodes, or do we have another one after that? That's really the only point being debated."

The debate's outcome will have little impact either way on the defect reduction section of the 1999 document, according to David Jensen, cochairman of the roadmap's defect reduction crosscut technology working group (TWG). "I've done a lot of work on this in the last four to six weeks," he said cautiously in early May. "I started with an interest in trying to set the defect targets based on what is now going to be a constant-die-size algorithm as opposed to an increasing-die-size algorithm, which was the case in 1997.

"In order to help understand the impact of two versus three years," he continued, "I went through a lot of analysis on defectivity levels and tried to use that as a basis for some of the data we had used in benchmarking the member companies of Sematech. I don't want to quote exact numbers, but from a defect perspective our data would say we could maintain yields at either a two- or a three-year cycle."

The revised 1998 document does away with the 0.15-µm technology node and moves the 0.13-µm node for DRAM half-pitch chips to 2002 from 2003, its previous spot in the 1997 roadmap. The 0.10- and 0.07-µm nodes were nudged up one year each to 2005 and 2008, respectively.

As Doering indicates, the debate has centered on whether to transfer the accelerated dates to the 1999 ITRS or stick with the original three-year intervals. The involved parties batted the issue around in April during a meeting held at the Semicon Europa trade show in Munich. The German meeting further highlighted the split that has developed between the microprocessor and DRAM camps. The MPU manufacturers have been pushing hard for two-year intervals, while their counterparts on the DRAM side have resisted the notion. The existing roadmaps have DRAMs as the driver, but some now believe that microprocessors should share the technology driver's seat with DRAMs.

"There are a lot of people on the MPU side who feel pretty strongly that the rate of progress is likely to be faster than the 1998 revision," notes Juri Matisoo, vice president of technology development for SIA, which is the official sponsoring agency for the roadmap. "The discussion in Munich centered quite a bit on whether in fact the early portion of it is likely to accelerate to two-year intervals. That's particularly true for the MPU folks and somewhat less true for the DRAM people. In Munich it was still left somewhat open as to what the final agreed-upon...technology nodes will be.

"I suspect that by the time of the Austin get-together [the issue] will have been settled," continues Matisoo, who called the German meeting "very successful." An open meeting for representatives from the U.S. chip industry only was set for June 2—3 in the Texas capital to discuss the 1999 document, he says.

The new document will have a more refined defect look, Jensen points out. "We're going to try to present defect budgets on a much finer level in the 1999 roadmap than in the 1997 version. The equipment list is much longer. Rather than a generic implanter, the 1999 version will show high- versus medium-current energy, or in etch it will show etch oxide and metal etch, that sort of thing. We're going to give a better granularity to the defect budgets."

Jensen and others involved in working on the 1999 edition speculate that tool suppliers may have trouble meeting a permanently accelerated schedule. Says Jensen: "From a yield perspective, based on historical learning rate data... accelerating to two years may be difficult for equipment suppliers to meet cost-effectively. Most of the yield learning is where we're sorting out process variations, and we're trying to fine-tune the process in order to maintain circuit performance. Likewise, we're trying to make the equipment as clean as possible. That phase is where we're going to target defect levels and get them indicated in the roadmap in terms of targets for suppliers. If we were to use a larger die size, those device targets could be a little bit higher. If we were to use a smaller chip size, they could be looser than they need to be. It's a kind of game in that respect." In a follow-up conversation, Jensen stressed, "We are able to learn fast enough on a three-year cycle to maintain the appropriate levels of yields."

Doering says that proponents of shifting to two-year intervals argue that for DRAM manufacturing in particular the quicker that chipmakers move to smaller linewidths the faster they reduce production costs. "Going to smaller feature sizes generally is going to let you pack either more bits on a chip or more chips on a wafer. Everything else being equal, and looking back historically, that has tended to save money."

Opponents, however, turn the argument around, Doering says. "The opposite point is being made by some that, indeed, even though doing those lithography shrinks historically has saved costs at the chip level, it may not continue to do so, because lithography tools and the materials are getting so expensive. It's not just the steppers, it's also the masks, and to some extent it's the photoresists, although that's still negligible. We may have gotten to the point of diminishing returns, where historically trying to pull this in at the shrink we may be surprised [to find] that the tool and the masks cost so much more that the cost, at best, levels. That's a hot topic right now."

Peeling back that onion one more layer, as he puts it, Doering says that some in the industry argue that shrinks can continue at the 193-nm wavelength level if they figure out "how to get the numerical aperture a little bit bigger and do a few more tricks.... So we're really saving some small incremental costs. Then there are other people who say it's going to be possible to do that by switching to 157 nm, and you just can't accelerate that fast." The risk, notes Doering, is that "the first [lithography] tool will be too expensive, and you'll suffer yield loss."

Comparing the 1998 revision with the 1999 ITRS, Doering says: "Basically if you look at DRAM half-pitch—which is what we're using as a single row on the map to characterize the nodes—in '98 we showed 180 nm for half-pitch in '99 and then 130 nm three years later in 2002, so there's a three-year gap there. Now, what's currently being discussed...is whether it's possible that the 130-nm node could be pulled up a year to 2001. That's the debate."

However, notes Jensen: "There is significant concern on a defect level and other related areas of accelerating to two years. That's definitely the case that, netted out, there's a greater likelihood of three years than two."

Jensen was asked whether he thinks tool suppliers would have equipment ready to meet a two-year schedule. "My suspicion," he replies, "is if we separated out the quote-unquote 'enhancements' like shrinks...from all the other components I bet the equipment suppliers would have a hard time meeting a two-year frequency. My belief has been, and analysis will bear this out, they're kind of on the hairy edge as it is, because when we show these [defect-learning rate] numbers extrapolated into the future for each technology node, suppliers would not be able to keep up without significant expense."

Some chipmakers, Intel among them, maintain that two-year intervals make sense, given the industry's traditional technological pace dictated by Moore's law. "If you look at the numbers, we must be on a two-year cycle, given our historical progression of technology to double functionality every two years," Jensen agrees. "That's just the way the numbers work; you can't do it any other way. The inference is if you go to a three-year cycle all the 'head room' is lost, and we start to slow things down.

"The main driver is probably lithography," he continues. "If litho basically just says, 'there's no way that's going to happen whether it's a requirement or not,' then the general inkling of the International Roadmap Committee is to go along."

Because this is the first international roadmap, Doering points out that the committee is inclined to respect the input of industries in Japan and South Korea. Both those regions, of course, have heavily invested in DRAMs, which have set the technological benchmark for the roadmap.

Doering notes that opinions on the technology node question have been "pretty evenly divided," and he finds that they tend "to be a little bit along regional lines. That makes [the debate] even more interesting. The different regions don't produce equal amounts of DRAMs any more. We have made the roadmap a little more detailed now; we used to have just one line for half-pitch DRAMs. Now we have DRAM and MPU and ASIC added in. Now that we've gotten down to that level of specificity product-wise I think everyone is going to respect the opinions of the people who are the biggest makers of most of those products, especially DRAMs, particularly the Japanese and Koreans."

The Munich meeting didn't uncover any new defect concerns, according to Doering, other than areas closely related to metrology. "I don't think we're approaching falling off a cliff as we make these lines a lot closer together and [we see] a lot of small particles that short out everything." On the metrology side of defect reduction, he adds, manufacturers "are running into a higher density of smaller particles."

Responding to Doering's comments, Jensen acknowledges that this aspect of metrology simply represents an ongoing problem. "From a defect metrology perspective a lot of tools have the capability in terms of providing a robust manufacturing-worthy detection capability. Where we fall off the cliff, so to speak, is at the 0.10-µm level. There are tools that can find the smaller defects, but they're not manufacturing-worthy from a throughput perspective.

"If you're going to do this type of lithography you have a problem with defect detection," Jensen adds. "You take a very big cycle-time hit, or you take a significant wafer-cost hit. Finding a high-speed, high-sensitivity tool is a problem."

The TWG cochairman points out, though, that the "performance of metrology is much better than what the defect budget is" in the 1994 and 1997 roadmaps. Results of the limited yield modeling done at Sematech and depicted in the 1997 document "are inconsistent with what we observe today."

Come early July, industry representatives from around the world will begin to put the finishing touches on the roadmap to meet the year-end deadline. "The international conference in Santa Clara is the last opportunity to collect input," Doering notes.

"One of the concerns that the SIA board of directors had when they agreed to do the international version was that having so many [geographical regions involved] might slow the whole process down," Matisoo says. "As of now that does not seem to be happening." In other words, the fully revised 1999 roadmap, he asserts, will be ready "for year-end '99 release."

Anyone interested in attending the international roadmap conference in Santa Clara, CA, July 8—9 may contact Sematech Meeting Services at 512/356-7437.

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