BUILDING COPPEROPOLIS

Implementing SMIF and auto ID to ensure high-volume copper processing integrity

William Fosnight, Dan Fritschen, and Ray Martin, Asyst Technologies

As chip making becomes more automated and copper processing relies more on automation software and automated tools, SMIF and auto ID can be integrated into tool automation systems.

The use of copper as a conductor in the new generation of ICs promises improved chip performance and reduced manufacturing costs. Below 0.25-µm design rules, interconnect resistance becomes a major physical challenge. Copper has been identified as a beneficial interconnect metal that can reduce resistance and capacitance time delay posed by smaller design rules.¹ Moreover, it offers a large potential cost savings advantage over current aluminum alloy wafer processing. Rather than using the metal-subtractive techniques associated with aluminum fill processing, leveraging dual-damascene copper wafer processing can reduce the number of process steps by 20% or more.² Nevertheless, despite all of the advantages, copper interconnects pose fundamental manufacturing issues that can greatly compromise process integrity and affect yield. One such issue is the risk of copper contamination.

One reason copper has not yet been accepted and used at high-volume levels is that copper atoms readily diffuse through silicon. Acting as a dopant, copper contamination, if not contained, can significantly alter the conductance of all contaminated regions, which can fatally affect semiconductor devices. Diffusion barriers have been greatly improved to prevent the migration of copper from one layer of a device to another.

The risk of copper contamination is particularly great during typical wafer processing functions. Mechanisms such as particle generation, physical contact, and dissolution are significant risk factors. Cross-contamination from other tools and wafer-handling mechanisms are additional means of copper contamination. These process-based contamination factors present the highest risk of contamination during front-end-of-line (FEOL) processing steps, such as wafer cleaning and stripping and thermal (furnace) applications. Copper contamination is not merely limited to copper wafer lines or their immediate areas but can also jeopardize entire facilities, including those in which aluminum processing lines are not physically isolated from copper processing lines and in which back-end-of-line (BEOL) steps can contaminate FEOL tools and wafers. While copper contamination does not necessarily affect the performance of processing tools or wafer-handling robots, it can negatively impact yield, especially at high-volume foundries where many different products are processed at the same time.

High-volume copper processing can be limited because the monitoring of copper contamination is largely a function of laboratory-based analytical systems, which do not lend themselves to in-line monitoring. Such analytical techniques as vapor phase decomposition—total reflection x-ray fluorescence (VPD-TXRF) and Fourier transform infrared (FTIR) spectroscopy are slow and often must be undertaken in off-line lab facilities. For example, in order to detect extremely low levels of copper contamination to 5 x 109 atoms/cm², which can negatively affect device functionality, it is necessary to remove wafers from the fab to an off-line lab facility to perform VPD-TXRF spectroscopy. Because this level of contamination cannot be monitored in-line, copper contamination can remain undetected until many wafers have been processed and fatal contamination has occurred—an unacceptable scenario in the high-yield, high-volume semiconductor manufacturing industry.

Interestingly, the complex ultraclean manufacturing methods involved in ongoing IC die shrinks can potentially be applied to reducing copper contamination. This article explains how the acute control of the immediate wafer environment and the wafer cassettes through standard mechanical interface (SMIF) technologies can lessen the risks associated with copper wafer processing. It also describes how this control method can promote the seamless adoption of a processing strategy to reduce the risk of copper cross-contamination and discusses how automated asset and lot identification (auto ID) can further reduce the risk of contamination by helping to prevent wafer misprocessing.

SMIF: A Tested Strategy

The manufacturing technologies that can be successfully implemented to contain and manage copper contamination are employed extensively by foundries, some of the most productive and profitable fabs in the world. By leveraging the proven environmental and automation controls offered by SMIF isolation, the contamination risks associated with copper wafer processing can be minimized, thus enabling the IC industry to overcome significant manufacturing concerns in the adoption of high-volume copper processing.

Figure 1: Airborne particles (>0.1 µm) in a conventional Class 1 fab (top), including particle bursts illustrated by graph spikes, are substantially higher than in a SMIF-configured Class 1000 foundry fab (bottom).

SMIF systems can contain copper contamination through isolation and the acute control of the wafer environment. SMIF pods and load, or input/output (I/O) ports, provide the closed-loop wafer-routing procedures that are required to isolate and physically contain copper contamination without the need for structural or facility barriers. Applying the wafer isolation capabilities of SMIF systems to copper processing enables chipmakers to achieve the same wafer environment control levels as those enjoyed by current SMIF users. Figure 1 illustrates that the number of airborne particles in a conventional Class 1 fab, including particle bursts, are substantially higher than in a SMIF-configured Class 1000 foundry fab. The acute control exercised by SMIF pods results in the virtual elimination of particle burst events. The SMIF pods' ability to control the wafer environment is significant, since wafers spend approximately 80% of their processing lifetimes in transport and storage. Figure 2 shows that particle levels on wafers stored in conventional boxes in Class 1 fabs are considerably higher than those on wafers stored in SMIF pods in Class 1 and Class 10,000 fabs.

Figure 2: Particle levels (>0.3 µm) on wafers stored for 24 hours in conventional boxes in Class 1 fabs are considerably higher than those on wafers stored in SMIF pods in Class 1 and Class 10,000 fabs.

SMIF systems such as that depicted in Figure 3 are also able to purge the wafer ambient and replace it with an inert environment, which can benefit copper processing. It is impossible to achieve this at the global facility level. Purging wafer pods helps to eliminate other forms of contamination, such as airborne molecular contaminants (AMCs) and corrosion. While nearly particle-free in the case of SMIF pods, the ambient environment in which wafers reside can include high levels of acid vapors, hydrocarbons, and various other gases, which can significantly alter wafer surfaces—especially metallic ones—or negatively react with other sensitive materials or gases. Purging the pods and replacing the highly variable ambient with clean dry air or nitrogen helps to eliminate the potentially damaging effects of AMCs.³

Figure 3: Series of stations in which inert wafer ambient at tool loadlocks is achieved by purging SMIF pods with nitrogen in conjunction with the ULPA-filtered recirculation of nitrogen at an automated buffer station. Photo courtesy of Asyst Technologies

SMIF and Copper Cross-Contamination

A significant risk in copper processing is copper cross-contamination, which can have severe repercussions for yield and tool operability. There is no clear way to clean a copper-contaminated FEOL wet sink, potentially rendering the tool inoperable for an indefinite period of time. Cross-contamination can result when a back-end wafer contaminates a front-end tool, when a front-end tool contaminated by a back-end wafer subsequently contaminates FEOL wafers, and when a back-end tool contaminates a front-end wafer. A front-end wafer exposed to a back-end carrier or tool can contaminate FEOL wafer carriers or tools. Moreover, airborne- or surface-transferred copper particles can contaminate FEOL wafers and tools.

In order to prevent cross-contamination, it is crucial to prevent BEOL wafers from entering an FEOL tool. SMIF systems effectively manage front- and back-end copper wafers by segmenting FEOL and BEOL pods and load ports. This strategy can be easily implemented in any SMIF manufacturing environment because of the adaptability of existing pods and load ports. SMIF systems protect against contamination by incorporating a mechanical interlock solution proposed by members of International Sematech as a standard for the segmented FEOL-BEOL processing of 300-mm wafers. This standard specifies "info pad" or pin-placement locations.⁴ Figure 4 is a schematic of a 300-mm wafer carrier bottom, illustrating mechanical interlock pin placements that distinguish back- from front-end pods. As shown in Figure 5, this mechanical interlock system makes it physically impossible for a BEOL pod to fit onto a FEOL load port, preventing the pod from opening and the wafers from being processed. Correct placement allows a wafer carrier to sit properly on a load port, enabling wafer processing. As a result, wafers residing in a front-end pod can be placed and processed only in front-end tools. A similar mechanical interlock scheme for 200-mm SMIF pods is available.

Figure 4: Schematic diagram detailing mechanical pin placements used to distinguish BEOL from FEOL carriers in order to reduce the risk of cross-contamination on 300-mm wafers. Illustration courtesy of Semi.

Figure 5: Incorrect pin and info pad placement interferes with carrier placement and prevents wafer processing, while correct placement allows a wafer carrier to sit properly on a load port, enabling wafer processing. Illustration courtesy of Semi.

The FEOL-BEOL strategy provides an effective physical safeguard to ensure copper processing integrity. Wafers can be transferred from front- to back-end pods via a wafer management system that sorts wafers at the end of FEOL processing. This ensures that BEOL wafers do not occupy FEOL pods and that FEOL wafers do not occupy BEOL pods. Another effective physical safeguard is the color-coding of wafer carriers. Figure 6, which shows amber-colored front-opening unified pods (FOUPs) used in 300-mm wafer processing, demonstrates that the entire pod housing or the pod handles can be color coded, providing distinct visual cues about the status of the wafers within.

Auto ID

While SMIF systems offer chipmakers effective physical safeguards against copper contamination, operators can manually override those safeguards. Auto ID serves as a process control solution, providing a critical dimension of support beyond color-coding, SMIF pods, and mechanical interlocks to prevent copper contamination. Leveraging automation software to control wafer routing, identify lots, load the SMIF pod, control process tools, and select process recipes helps to further contain and minimize the risks of copper contamination.

Chipmakers have used auto ID technologies combined with SMIF pods to enhance contamination control and eliminate operator errors associated with misprocessing, serving as a "lock- and-key" solution to wafer processing. In conjunction with SMIF systems, auto ID has proven to be an effective strategy for ensuring that the correct wafers are always processed in the correct pods and for ensuring that the correct pods are always processed on the correct tools. These capabilities are the essence of successful copper management.

Using radio-frequency technologies, bar codes, or infrared-based electronic run card technologies to maintain and provide specific lot, processing, and tool information, fabs can achieve a critical layer of security against contamination through the advanced automated identification of lots combined with equipment management software. Such a combined system is depicted in Figure 7, which shows an operator who has loaded a 200-mm SMIF pod onto an automated load port. Only after the pod and its contents have been automatically validated via the information contained on the attached electronic run card or tag can the operator initiate processing. Combined with the physical safeguard potentials of SMIF pods, auto ID can provide the most effective strategy against copper contamination, helping to eliminate the risks of low yields or yield crashes because of copper contamination.

Figure 6: Amber-colored front-opening unified pods (FOUPs), shown loaded onto a 300-mm I/O port, are used in a fab for 300-mm wafer processing.

Figure 7: After an operator has loaded a 200-mm SMIF pod onto an automated load port and automatic validation of the pod and its contents has taken place via the information on the attached electronic run card or tag, processing can begin. Photos courtesy of Asyst Technologies.

Electronic run cards or tags can be designed to store detailed lot information, such as lot ID, routing instructions, process recipes, and wafer maps, and remain with a wafer lot for the duration of processing. When an operator transports a copper wafer lot to a process tool in this automation scenario, the system immediately verifies the lot ID and status using the data stored in the electronic run card. Immediate and automatic lot validation detects whether a FEOL pod has been brought to the wrong front-end tool, thus preventing the pod from opening. More important, this system prevents contamination even if the SMIF system's physical safeguards have been manually overridden. This lot validation solution, combining software and auto ID, can be vital to ensuring copper processing integrity.

During chemical mechanical planarization (CMP) in copper processing, the primary objective is to prevent particles (including copper) from making their way to the next sequence of tools. To address this issue, fabs have proposed the use of dedicated CMP-area pods. Wafers from these pods are returned to a BEOL pod after post-CMP cleaning. Auto ID can be further leveraged at this point to segregate CMP pods from back-end pods. This CMP wafer management tactic, combined with the FEOL-BEOL isolation strategy, actively contains potential copper contaminants generated during the more volatile processes, effectively decreasing the risk of copper cross-contamination.

Conclusion

Advances in device technology depend on advances in manufacturing capabilities. Copper interconnects will give rise to a new generation of devices and, in turn, new electronics capabilities. In the past, manufacturing advances followed device technology innovation. Fortunately for copper processing, the fundamental manufacturing technologies and strategies required for high-volume processing already exist in the form of SMIF isolation and auto ID strategies. Moreover, these strategies have been used extensively to control contamination and defectivity, optimize productivity, and help meet yield goals at some of the world's most successful foundries.

As semiconductor manufacturing becomes more automated, copper wafer processing will rely more on the manufacturing integrity offered by the integration of automation software and tool-automated front ends. In this manufacturing strategy, contamination safeguards such as SMIF systems and auto ID—regardless of device type and interconnect material—can be integrated into future tool automation systems, helping to reduce or eliminate the risk of contamination and misprocessing throughout the entire IC manufacturing process.

References

1. XW Lin and D Pramanik, "Future Interconnect Technologies and Copper Metallization," Solid State Technology 41, no. 10 (1998): 63–79.

2. P Singer, "Tantalum, Copper and Damascene: The Future of Interconnects," Semiconductor International 21, no. 6 (1998): 91–98.

3. A Bonora, "There and Back Again," Solid State Technology 40, no. 5 (1997): 141–149.

4. SEMI E15.1, Provisional Specification for 300-mm Tool Load Port.

William Fosnight is Asyst's director of strategic technology in Austin, TX, where he manages the company's relationships with Sematech, I300I, and SEMI. His responsibilities include the development of wafer and reticle transport, storage, and handling products, including carriers, equipment interfaces, and automation systems. Before joining Asyst, Fosnight was with Digital Semiconductor (Hudson, MA), where his responsibilities included the development and implementation of strategies needed to meet the contamination control requirements of advanced microprocessor manufacturing. Fosnight holds a BS in mechanical engineering from Ohio State University (Columbus) and an MS in mechanical engineering from Rensselaer Polytechnic Institute (Troy, NY). He recently contributed to the defect reduction and factory integration sections of the 1997 SIA National Technology Roadmap for Semiconductors. (Fosnight can be reached at 510/661-5000 or wfosnight@asyst.com.)

Dan Fritschen is Asyst's auto ID product marketing manager, based in Fremont, CA. Before joining Asyst, Fritschen worked in the automation industry specializing in electronics and flat-panel display assembly. He is the author of several papers and seminar curriculum texts focusing on automated manufacturing and electronic component assembly technologies. He studied mechanical engineering at the University of Kansas (Lawrence) and has spent the last 10 years working in the factory automation industry. (Fritschen can be reached at 510/661-5000 or dfritschen@asyst.com.)

Ray Martin is Asyst's director of product marketing for SMIF products and oversees product management for 200-mm, 300-mm, and reticle SMIF load ports and pods. Before joining Asyst in 1995, he worked for Intel for more than 13 years, including as a plasma etch process engineer. He also supported Sematech as an Intel representative in the quality and contamination-free manufacturing groups. Martin holds a bachelor's degree in industrial engineering from Georgia Tech (Atlanta) and a master's degree in engineering management from Santa Clara University (CA). (Martin can be reached at 510/661-5000 or rmartin@asyst.com.)

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