Defect prevention and elimination: Where the rubber hits the road(map)

David Jensen, AMD/Sematech; and William Fosnight, Asyst Technologies

(Fifth and final installment in the series)

I n the previous Mapping the Roadmap installments, we outlined necessary technology requirements in yield modeling,¹ defect detection,² and defect sources and mechanisms³ for improved and accelerated yield learning⁴ as proposed by the SIA's National Technology Roadmap for Semiconductors (NTRS).⁵ This fifth and final installment will review the necessary technology requirements for the prevention and elimination of yield-limiting defects. These requirements encompass traditional contamination control topics of ultraclean processing materials and environments as well as newer areas of opportunity, including process-to-process and design-to-process interactions, and process parameter control.

There must be a fundamental understanding of the impact of individual contaminants on product yield and device performance. Photo Courtesy of St Microelectronics.

In many ways yield improvement efforts do not become meaningful until an action can be taken to adjust or change something that ultimately adversely affects yield. Modeling, simulation, inspection, testing, failure analysis, and the like are necessary and meaningful only when they support root-cause assessment of a yield loss mechanism so the appropriate action can be taken to prevent the defect from occurring again. These actions form the basis of defect prevention and elimination (DPE) as outlined in the NTRS. As an example, this section outlines metallic levels in prediffusion clean chemicals necessary to achieve surface concentrations that will not effect gate oxide breakdown.⁶ As much as possible these DPE technology requirements are based on the known failure or yield-impact mechanisms dictated by other areas of the roadmap. Many of these requirements are not validated, and therein lies the most difficult DPE challenge.

Difficult Challenges

The most difficult DPE challenge is the correlation and validation of trace impurity specifications in process-critical environments and materials. Test structures and advanced modeling are needed to determine the impact of trace metallics, ions, and organics on device performance, reliability, and yield. The issue of what degree of fluid (chemical, gas, air, water) purity is necessary for each technology generation has been a chronic problem in the semiconductor industry. New fab construction has continually raised questions about the degree of sophistication (and ultimately investment) necessary to deliver these environments to the wafer processing locality. It was once generally believed that each new technology generation would require an order of magnitude improvement in process-critical material purity. A key message of the current roadmap tempers this thinking to suggest such levels of improvement in process-critical fluid purities do not appear to be necessary well into the sub-100-nm regime. There must be a fundamental understanding of the impact of individual contaminants on product yield and device performance in order to justify the accompanying improvements in chemical/ gas manufacturing, distribution and control technologies, technologies that support two to three orders of magnitude higher-purity materials than those measured within processing environments. A fundamental understanding of impurity impact is required not only to prevent excessive cost caused by overspecification, but also to provide an early warning of the need for tighter specifications.

Figure 1: Defect reduction learning cycle.⁴

The rest of this article reviews the background of each DPE area, comments on potential challenges and enhancements, and presents technology requirements and potential solutions. To illustrate these topics, Figure 1 shows DPE areas in relation to a typical defect reduction learning cycle, while Figures 2 and 3 delineate potential solutions for process materials and wafer environment control, and process equipment and parameter control, respectively, according to the NTRS.

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Figure 2: Potential solutions for wafer environment control and critical materials according to the NTRS.

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Figure 3: Potential solutions for defect prevention and elimination in process equipment and parameter control according to the NTRS.

Process Materials

The cleanliness of raw materials that act chemically to produce conditions of deposition, etch, or surface conditioning is integral to high-yielding semiconductor manufacturing. Because of the enormous emphasis placed on ultrapure water, bulk and specialty gases, liquid chemicals, and tool and chamber materials (especially those that come into contact with the product) in the last 5—10 years, these process-critical materials are thought to contribute a very small portion of yield-limiting particulate contamination. Additionally, trace ionic contaminants within certain critical chemicals have been reduced to levels that are believed to be adequate for meeting requirements for the next two to three technology nodes. This is evident in factories being built that will start with 180-nm technology and support two to three nodes without significant investment in upgraded delivery systems.

Critical particle size is based on half the technology node design rule, with all defect densities normalized to this size. However, this critical size will not always result in a killer defect, since generally the back end of the line (interconnect) has looser design rules than the front end, and actual kill ratios depend on additional factors such as composition, critical area, and the like. Similarly, the front end may be even more sensitive, with 30—40-Å gate oxide thickness for example. Particle levels per volume for gases, chemicals, and DI water have been held constant at this critical particle size.

Assuming an x^—2.7 power law relationship, this means a cleanliness increase of approximately 2x per generation, or ~80x from the 250- to the 50-nm technology node. The measurement and monitoring of particles at the critical size is thus inferred, but monitoring of larger-size particles can be done with requirements scaling according to the power law. Many factors—filtration, equipment cleanliness, wafer cleanliness, process chemistry ambient, and particle counting efficiency—affect the ability to achieve these particle levels. Therefore it is difficult to definitively indicate the state of the art (i.e., the color of the cells) in the NTRS technology requirements table (Table I). The particle levels have thus been coded yellow across the seven technology nodes represented by the roadmap. In other words, the consensus of the roadmap committee was that given a comprehensive particle management program, these levels could be achieved. The ultrapure water particle levels were incorrectly color coded as red and have been corrected here as well as in the 1998 electronic update of the roadmap to be used for the basis of the 1999 revision of the NTRS. Table I lists these particle levels as well as other technology requirements for process-critical materials and wafer environment control.

Table I: Technology requirements for wafer environment control and process-critical materials according to the NTRS.

The technology requirements for ultrapure water stress the importance of low levels of particles, total silica (colloidal plus dissolved), and ionics. The dissolved oxygen content must be controlled for rinsing after HF-last cleans on bare silicon. Until tools operate in a nitrogen environment, controlling oxygen below 1 ppb is unlikely to be practical. Even in leading-edge fab design and state-of-the-art ultrapure water production, single-digit dissolved oxygen levels are typical. Sub-10-ppb fluorine levels may not be possible in PVDF piping. With the exception of upset events, typical DI water systems run at virtually 0 CFU per liter of bacteria because of limitations in detection technology. These systems are not sterile systems, however, and analytical technology (e.g., polymerase chain reaction⁷) will have to be deployed to characterize ultratrace levels of bacteria (both viable and nonviable). Recycling and reclaiming initiatives must drive improvements in rapid on-line analytical technology, especially detection of organics, to ensure recycled water has the same purity as single-pass water. Levels of total oxidizable carbon (TOC) do not reflect what is achievable in state-of-the-art water plants. Comments have been received that these levels would be more appropriate as 2, 2, 1, 1, <1, <1, and <1 ppb, respectively, across the seven technology nodes represented in the roadmap and have been changed accordingly in Table I. Single-digit TOC levels are commonplace in leading-edge semiconductor manufacturing plants although strong evidence does not exist in the open literature defending the need for such specifications. Likewise, the most exacting requirements are only necessary for final rinses prior to critical surface preparation steps. For pregate, prepoly, premetal, presilicide, precontact, and pretrench fill, an improvement of ~5x is expected to be necessary over the seven NTRS technology nodes.⁶ However, the roadmap generally tries to prescribe current technology requirements aligned with state-of-the-art capability. As such, these tighter specifications will be reviewed for inclusion in the next revision.

For process chemicals, prediffusion cleaning requirements are the driving force toward the most aggressive impurity levels. These bulk levels have been relaxed compared with the 1994 roadmap⁸ to correspond with the specification of surface levels of metallics.⁶ This evolution of the surface levels of critical metallics shows that only an ~5x improvement will be required over the next 15 years. The corresponding bulk impurity levels indicate that an ~10x improvement will be necessary over the next 15 years with solutions existing to achieve these levels in critical RCA chemicals (HF, H_²O_², NH_⁴OH) down to <50 ppt for copper and iron.

Liquid particle counting technology presents a critical challenge below 90 nm. For HF-last or SC-1 last cleans, the use of novel chemistries (complexants, pH adjustments) may be required to meet the surface preparation requirements. There is still a critical need to clearly understand the chemical and physical mechanisms of contaminant deposition from bulk to surface for various chemical mixtures, individual metallics, and differing surface conditions, and ultimately correlate these levels to yield and device performance.

While major changes are not expected for nitrogen, oxygen, argon, hydrogen, and other bulk ambient gases, in-line nonintrusive particle measurements at the critical size in these gases as well as in specialty gases will be a significant challenge. Although current technology can be extended to meet the measurement requirements at the point of use (POU), continuous particle monitoring in each specialty gas line would add substantial costs to factory infrastructure. Additionally, the volume of gas required to obtain statistically representative information—3 to 10 times the unit volume specified—would result in venting significant amounts of the specialty gas, thus increasing cost. For specialty gases the sensitivity to contamination may vary significantly by process. POU filters, and in some cases purifiers and gas generators, can be used to meet the most stringent requirements. In metal etchants Sematech has supported studies that indicate high levels (hundreds of parts per million) of gaseous contaminants such as H^₂O, O^₂, CO^₂, and CH^₄ result in little impact on etch rate or selectivity. This supports the notion that device impacts must be studied to validate any need for increased purity. System concerns (i.e., corrosion potential) may lead process concerns in seeking higher purities. Conversely, for some deposition gases (e.g., WF^₆) these types of contaminants can produce detrimental processing effects. Further studies may only prove necessary for gate etch, given the reduced use of metal etchants as circuit interconnect technology makes the transition from subtractive metal etch to inlaid dual damascene technology. Trace impurity analytical technology for process-critical materials is needed so purity levels at the point of use can be better understood.

It will be increasingly important to have impurity specifications for such novel processing materials as sputtering targets, oxides, CMP slurries, low- and high-k dielectric materials, and novel barrier and conductor metals (e.g., copper and tantalum). Original measurement techniques and impact studies are also required to ensure that these materials are produced with the impurity specs that meet technology requirements.

Wafer Environment Control

As devices enter the realm of nanometer-scaled features, the ambient wafer environment must be controlled. Particle contamination, temperature, and humidity have been the traditional focus areas of wafer environment control efforts, with a more recent emphasis placed on molecular contamination control. As one report noted, "On a mass basis, the abundance of vapor-phase species is many orders of magnitude larger than the total particle mass in a typical Class 10 cleanroom."⁹

The control of moleculars is used selectively by some manufacturers to extend the viable duration of work-in-process (WIP) storage as well as process windows. The deployment of molecular control varies significantly from one manufacturer to another. Many fabs use nitrogen desiccator cabinets for WIP storage at critical process steps. Generally, the percentage of process steps affected by moleculars should increase. Whether a company now deploys molecular contamination control or not, it will become an enabling factor within the next few process generations.

Wafer isolation technology, a form of environmental control in which the wafer is isolated from the cleanroom ambient, is one means to better control particulate and molecular contaminants. Because of this factor as well as the ability of wafer isolation technology to facilitate fab automation, the International 300-mm Initiative (I300I) and nearly all Japanese IC manufacturers have chosen a closed carrier or pod, standard tool interface, and minienvironment architecture for 300-mm wafer processing. While isolation technology offers extended capabilities, the needs of the wafer environment must be fully understood. Isolating the wafers does not completely resolve the issues—clean materials and optimized designs are still critically important.

A key challenge of wafer environment control is determining which contaminants need to be controlled and to what level. Zeroing in on ambient defect sources and mechanisms represents a substantial challenge. For example, the ambient contribution of contamination relative to the required wafer-surface preparation states must be understood. The introduction of new materials, new chemicals, and evolving processes further challenges the ability to determine the appropriate level of ambient contamination. Wafer environment control requirements are based on the requirements of two corresponding areas of the roadmap. The airborne particle concentration values are derived from the wafer-handling requirement of the yield model, while the airborne molecular contaminant (AMC) values are drawn from the technology requirements for critical processes in the roadmap. The manner in which the particle and molecular roadmap values were determined follows. (Although these values have not been validated, the assumptions made and methods used are carefully documented in order to foster
future refinement.)

The airborne particle contamination roadmap levels were backcalculated from the acceptable surface particle contamination roadmap levels for wafer handling. This implies that all particles added outside of the processing environments as part of the storage, transportation, and handling of the wafers come from the wafers' ambient environment. Deposition
velocity (meters per hour) is a factor that predicts the surface arrival rate of particles on a wafer based on the airborne particle concentration.

Surface deposition (particles/m²/hr) = deposition velocity (m/hr) x airborne particle concentration (particles/m³).

The values of deposition velocity have been derived theoretically and validated empirically.^10—12 Deposition velocity varies with particle size, airflow velocity, and electrostatic charge. A moderately conservative value of 0.33 m/hr was chosen for the roadmap. This deposition velocity results in a surface arrival rate of 1 particle/m²/hr for every 3 particles/m³ airborne. The airborne particle concentration roadmap values were thus backcalculated from:

where:

In an analogous manner, the AMC limits were backcalculated from the wafer surface prep states. In this case, a 1-hour wafer exposure time and starting surface concentration of zero are assumed. The surface arrival rate of molecular contaminants is given as:

The airborne molecular concentration roadmap values were thus backcalculated from:

where:

Allowable surface concentrations are taken from the following portions of the roadmap: lithography—lithography roadmap; gate metals and organics—surface prep FEOL metallics and organics; and salicidation and contact, acids and bases—surface prep BEOL anions and metallics.

The following examples show how the airborne particulate and molecular contaminant levels for the roadmap were calculated. The airborne particle contamination requirement for 250-nm devices, assuming 300 process steps, a wafer exposure of 1000 hours, and a wafer-handling requirement of 30 particles/m²/step, is calculated as:

The base organic contamination requirement for salicidation assuming Na⁺ and a sticking coefficient of E = 1 x 10^—6 is:

When converted to pptM, it becomes:

As all of these equations are linear, users of the roadmap may scale with their assumed values accordingly.

Several potential solutions have been proposed to develop a better understanding of wafer environment control requirements and to meet these requirements. The first solution is advanced AMC deposition models accompanied by surface chemistry models. The current deposition model is an order of magnitude approximation. It will be even more important to understand which molecular species react with the various materials and processes. Once this is understood, there should be two basic means to resolve molecular contamination issues: either make the materials or processes tolerant to the contaminant, or eliminate the contaminant from the environment. An example of the former has been the development of deep-ultraviolet (DUV) photoresists with low sensitivity to ambient fugitive amines. If this type of solution is not possible, then an understanding of the surface chemistry will permit identification of the troublesome molecular species as well as ascertaining at what level those moleculars must be controlled or eliminated. In order to validate the molecular deposition and surface chemistry models, the availability of accurate, portable, real-time, and affordable analytical monitoring tools will be critical to obtaining needed data. Of equal importance to these analytical tools will be standard sampling and measurement techniques.

While wafer isolation techniques have been shown to meet the particle contamination requirements for geometries down to at least 100 nm, more focus is needed on understanding and eliminating molecular contaminants. There are four proposed potential phases for molecular contamination control:

• Development of noncontaminating materials for use in the cleanroom and wafer isolation systems.

• Deployment of nonabsorbing materials that do not promote cross-contamination between process steps or wafers.

• Deployment of inert or selectively filtered environments to displace and diffuse molecular contaminants.

• Development of systems that actively remove or trap contaminants within the environment.

As wafer isolation technologies evolve, material selection and design of carriers and enclosures will be critical not only because of how they perform in isolating the wafers from the ambient, but also for how they perform in not contributing contaminants themselves. In addition, the materials and designs must not promote cross-contamination between processes. Seal technology and low-outgassing, nonadsorbing materials must continue to evolve.

The third and fourth phases will likely make use of pods with inert environments to transport and store wafers. Pregate and precontact cleans and salicidation are cited as processes that will first require this capability. While closed-carrier purging systems exist and are evolving, tool environments that may need to become inert, such as wet sink end-stations, present a challenge. Purged pods are also being considered as a way to solve other related issues, such as:

• Reducing the introduction of moisture into vacuum loadlock tools, thereby decreasing contamination and loadlock pumpdown times.

• Facilitating cooling of wafers exiting from process tools, thereby allowing decreased cycle times.

• Preventing process-generated particles from being deposited onto wafers queued in the pod.

Design-to-Process Interactions

The relationship between device design and process capabilities is critical. Communication of data and management of information will be key enablers to optimize designs for yield, with clear and consistent information shared between the design and process stages. There must be standard test structures so the mechanisms by which processes and device structures interact can be determined. Once these mechanisms are understood, device design ground rules may be established that decrease process sensitivity. Cycles of process sensitivity analysis and reduction will be critical to advancing device design and yield.

While real process data are critical, they are often expensive and time-consuming to obtain. Process and device modeling can complement and leverage the value of these data. For example, defect sensitivity analysis and layout modification strategies are common in the industry and result in optimized layouts that reduce fault probabilities.¹³ These design and process capability interactions will have to become commonplace and automated so that designs at future technology nodes can realize true design for manufacturability. The key importance of process data is to help validate these models. The need to refine process parameters and interactions in models as opposed to doing the same in process tools will become increasingly important.

It is critical that communication be strengthened between device designers, process engineers, and manufacturing personnel so the required cycles of learning can be achieved. Successful communication may require active programs in integrated yield management.

Process-to-Process Interactions

There are various forms of process interactions, such as the direct, physical effect of one process on another, or others. These interactions may cause geometric variations, chemical reactions, and the like. Clearly it is not possible to concentrate on just one process without understanding its interactions with upstream or downstream processes. An example of this is how photoresist thickness and contact density can affect the residue level inside a via or contact. The use of advanced process control technologies and algorithms will prove critical in preventing these types of defect mechanisms. Run-to-run controllers are very useful in minimizing process variation, reducing scrap and increasing overall equipment effectiveness. A CMP run-to-run controller reduced nonuniformity variation by ~90% through the use of in situ film-thickness measurement and closed-loop control.¹⁴

Process monitoring will play a key role in the detection, understanding, and elimination of unwanted process interactions. Photo by Ed Shvartzman.

Another type of process interaction may be caused by more indirect cross-contamination, which can occur in many ways. Intertool cross-contamination may be waferborne, carrierborne, or airborne. Waferborne cross-contamination may arise as moisture, solvents, or other materials left on the wafer from one process degrade the performance of a subsequent process. Examples include copper cross-contamination or the effect of moisture in photoresist on a metal etch process. Similarly, the wafer environment of one process tool may be transported inside closed carriers to other tools, or exchanges of contaminants may occur between the carrier and wafers. Finally, airborne intertool cross-contamination may result from materials transported through the cleanroom ambient. An example of this is the effect of amines used in the fab on DUV lithography. Intratool cross-contamination may occur between "processes" within a particular piece of process equipment. For example, cluster tools and wet sinks must be carefully designed to ensure that their modules do not transfer any contaminants that degrade the performance of adjacent modules.

In order to detect, understand, and eliminate unwanted process interactions, process monitoring will need to play a key role. The appropriate sensors and data must be available, along with an appropriate information management system to correlate process parameters to upstream and downstream parameters and yield. Additional data alone will not be sufficient. Smart inter- and intratool statistical process control (SPC) will be the enabler of appropriate process specifications and metrology step reductions. Finally, communication between process developers and engineers will be increasingly critical as new processes and materials are introduced into ever-more-sensitive process sequences.

Process Equipment

Defect reduction in process equipment remains paramount to achieving defect density goals. Leading-edge high-volume manufacturers must execute approximately 9 out of 10 process steps with zero killer-defect adders in order to achieve competitive yields. Solutions and technology developments should provide major enhancement capabilities in the next 3—5 years and enable cost-effective, high-volume manufacturing for 130- to 100-nm devices. Chamber cleaning will be a technology enabler in this respect. New cleaning chemistries, in situ chamber cleanliness monitoring, materials development, and other techniques will help run-to-run chamber cleanliness and dramatically reduce the frequency of chamber wet cleans. Supporting improved chamber cleaning technologies will be improved parts cleaning techniques. These developments will help increase equipment utilization. Particle avoidance techniques based on empirical findings, such as O-ring material selection, gas flow and temperature management, and wafer chuck optimization, will continue to play a key role in meeting defect densities. However, more fundamental understanding of reactor contamination formation, transport, and deposition will be needed to enhance current equipment and process design. These fundamental physical, chemical, and plasma reactor contamination models must be employed in future equipment and process designs.

Equipment defect targets are primarily based on horizontal scaling. Parametric sensitivities and vertical faults, particularly when they apply to the gate stack, metallic and other nonvisual contaminants, need to be understood. An increased emphasis on reduced backside wafer contamination will drive both measurement technology and fundamental changes in equipment. Metal and particle cross-contamination from the backside of one wafer to the frontside of the next, hot spots and depth of focus in lithography, and "punch-through" on electrostatic chucks are all examples of issues that must be addressed in future tools.

Figure 4: SEM images of wafer defects and potential root sources from chamber parts and materials in a metallization process.

Programs to trace the source of wafer defects to tool conditions or materials will grow in importance in the development phases of new equipment and processes. Figure 4 shows several examples of wafer defects and the potential sources of these defects from chamber parts and materials in a metallization process.

Conclusion

There are countless means by which yield loss can occur in today's semiconductor manufacturing environment. The prevention and elimination of these defects through improved process materials, process equipment, and wafer environment; optimized parameter control and process interactions; and circuit design for manufacturability form the basis of actionable defect reduction activity according to the NTRS. This expanded view of how future technologies can be enabled and remain profitable through aggressive, preventive defect reduction should lead to more definitive technology requirements in future roadmap revisions. The authors encourage collaboration among design, test, process, integration, and yield personnel as well as equipment users and suppliers to forecast these new requirements so that appropriate and timely R&D investments can be made.

Acknowledgments

Portions of this article are adapted from The National Technology Roadmap for Semiconductors 1997 revision. Used with permission. We also want to acknowledge the following DR CCTWG members who participated on the DPE sub-TWG: Bob Blewer, Susan Cohen, Lindsey Hall, Zach Hatcher, Devon Kinkead, James McAndrew, Charlie Peterson, Ralph J. Richardson, Jennifer Sees, and Farhang Shadman. Additionally, the authors would like to especially acknowledge the efforts of Susan Cohen, who served as cochair of the DPE sub-TWG while at Sematech acting as CFM program manager.

References

1. Dance D, Jensen D, and Collica R, "Developing Yield Modeling and Defect Budgeting for 0.25 µm and Beyond," MICRO, 16(3):51—61, 1998.

2. Weber C, Jensen D, and Hirleman ED, "What Drives Defect Detection Technology?" MICRO, 16(6):51—75, 1998.

3. Gross C, Tobin K, Jensen D, and Mehta D, "Assessing Future Technology Requirements for Rapid Isolation and Sourcing of Faults," MICRO, 16(7):57—68, 1998.

4. Jensen D, Gross C, and Mehta D, "New Industry Document Explores Defect Reduction Technology Challenges," MICRO, 16(1):35—44, 1998.

5. The National Technology Roadmap for Semiconductors, San Jose, SIA, 1997.

6. The National Technology Roadmap for Semiconductors, San Jose, SIA, p 68, 1997.

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209—224, 1990.

12. Fosnight WJ, Gross VP, Murray KD, and Wang RD, "Deposition of 0.1 to 1.0 Micron Particles, Including Electrostatic Effects, onto Silicon Monitor Wafers (Experimental)," in Microcontamination Conference Proceedings, Santa Monica, CA, Canon Communications, pp 148—161, 1993.

13. Waring TG, Allan GA, and Walton AJ, "Integration of DFM Techniques and Design Automation," in Proceedings of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, New York, IEEE, pp 59—67, 1996.

14. Moyne J, et al., "Integration of Run-to-Run Control into Existing and Next-Generation Chemical-Mechanical-Planarization Tools," presented at Sematech AEC/APC Workshop IX, Lake Tahoe, September 1997.

David Jensen is program manager for defect reduction technology at Sematech, Austin, TX. He is an Advanced Micro Devices assignee and while there, as a member of the technical staff, his primary responsibilities were development and deployment of contamination-free manufacturing strategies. Before joining AMD, Jensen was at Digital Semiconductor for five years, where he was engineering supervisor of the Fab 6 CFM group. He served as cochair of the DR CCTWG for the 1997 revision of the SIA NTRS. He has also worked extensively in the semiconductor process equipment industry for ASM America and Spectrum CVD, holding numerous positions in design and engineering with emphasis on contamination control in process equipment. He has written numerous papers and has presented widely on contamination control and defect reduction technology. Jensen holds a BS in mechanical engineering from Arizona State University (Tempe). (Jensen can be reached at 512/356-3756 or david.jensen@sematech.org.)

William Fosnight is director of strategic technology at Asyst Technologies (Fremont, CA). He is located in Austin, TX, where he manages Asyst's relationship with Sematech, I300I, and SEMI. His responsibilities include the development of 300-mm wafer transport, storage, and handling products, including carriers, equipment interfaces, and automation systems. Before joining Asyst, he worked for Digital Semiconductor (Hudson, MA), where his responsibilities included the development and implementation of strategies to meet the contamination control requirements of advanced microprocessor manufacturing. Before joining Digital, he was involved with contamination control and wafer isolation studies at IBM (Burlington, VT). Fosnight has BS and MS degrees in mechanical engineering from Ohio State University and Rensselaer Polytechnic Institute, respectively. He recently contributed to the defect reduction and factory integration sections of the NTRS. (Fosnight can be reached at 512/ 306-1083.)

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