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PROCESS EQUIPMENT—RESIST REMOVALEliminating heavily implanted resist in sub-0.25-µm devicesAndy Kirkpatrick, Neil Fernandes, and Tinal Uk, GaSonics International; and Gary Patrizi, Philips Semiconductor As device design keeps pace with Moore's Law, IC manufacturers strive to improve yields and reduce costs. Defect control and overall equipment effectiveness (OEE) have become key elements in the pursuit of profitability. Coincidentally, new challenges in photoresist removal are emerging as device geometries shrink and new materials and manufacturing methods are introduced. The removal of implanted resist is one of the most important of these challenges. Although it involves relatively few mask steps (10—15%), the effective, efficient removal of damaged resist with minimal plasma damage to the wafer has a profound effect on yields, productivity, and OEE. The precise control of dopant depth and profile in the semiconductor substrate is a growing trend. Variations in dose, acceleration energy, and ion beam current control the concentration and depth of the dopant that is implanted through a patterned resist mask. The resist surface, however, hardens during the implant process, making the resist film difficult to remove. Implant doses >1 x 1015 atoms/cm2 and energies >50 keV accelerate the formation of this carbonized skin on top of the resist. Higher implant energies and currents as well as increasing resist coverage make removal even harder. Problems associated with implanted resist removal using conventional oxygen/nitrogen chemistry include long process times, resist popping, oxide residues, and unashed resist fragments. Fluorinated chemistry, a common solution to some of these problems, generates additional difficulties such as lifting and oxide loss. Other processing alternatives require expensive pretreatment or posttreatment processes and can even damage the wafer. As a result, innovative, cost-effective techniques are needed to process clean, damage-free wafers with acceptable oxide loss. The Root Cause The implant process damages the resist, causing some of the carbon-hydrogen bonds to release hydrogen and form carbon-carbon bonds, creating a cross-linked amorphous carbon compound with a graphitelike structure. After ion implant, the resist consists of two distinct layers—the carbonized layer or skin and the bulk resist. The implant species will also be imbedded in the carbon layer. For example, arsenic implant doses of about 2 x 1015 atoms/cm2 will result in about 1% arsenic in the carbon layer. The thickness of this carbonized layer is a function of the implant species, voltage, dose, and current. The underlying layer is bulk resist, which, as Figure 1 shows, typically has a high solvent content.
The thickness of the layer can be measured empirically by plotting resist thickness versus time and observing the "knee" of the graph, as depicted in Figure 2. The removal rate increases markedly by shifting from the crust to the bulk removal. The thickness (Ts) can also be closely approximated using the following formula: Ts = 491.0D — 0.2462(W x E) — 66.02W + 35.42E where D is the dose in units of 1015 atoms/cm2, E is the energy in kiloelectronvolts, and W is the atomic weight in atomic mass units. Although ascertaining the thickness is generally useful, it is especially helpful in process development when end-point capability is not available or when a time limit must be established on end point—controlled process steps.
The hardened skin prevents migration of photoactive agents, escaping solvent, evolved hydrogen, and other volatiles from the bulk resist. It is critical to control the resist removal temperature during the elimination of this layer to prevent exceeding the bubble point of these volatile components. If this point is exceeded, the crust layer will explode and spray crust fragments; this phenomenon is called popping (see Figure 3). The severity of the resultant popping is pattern dependent. Large resist areas will have little edge area without a skin to vent the volatile compounds, which results in the development of more popping residues than in smaller resist areas, which allow the volatiles to escape through their larger edge areas, as shown in Figure 4. Dopant and Oxide Residues Several types of residues can remain after implanted resist has been removed. As discussed, popping refers to residues from the carbonized skin breaking up and not being eliminated during processing. These residues can be left on the wafer and the chamber sidewalls. Although popping can be minimized by keeping the wafer process temperature below the resist bake temperature (typically 120°C), this can also result in long process times and significantly reduced OEE.
Dopant residues, which are oxides of the species, can be time dependent in appearance because of their hydrophylic nature. Oxidelike residue concentration and composition depend on pattern coverage, resist composition, implantation processes, and type of implant system. Figure 5 illustrates how some of the residues also relate to the sputtering of oxide during high-current implant. The residues worsen as the device geometries shrink and are only visible under a scanning electron microscope (SEM) (see Figure 6).
Line Lifting and Oxide Loss For device geometries <0.25 µm, the use of a fluorine-based chemistry requires additional care to avoid line lifting, which occurs if the fluorine concentration exceeds a certain pattern-dependent percentage. Since fluorine species lower the activation energy for oxygen/nitrogen resist removal, the difference in removal rate between the carbonized resist skin and the underlying resist layer widens, especially when the wafer temperature is kept below 150°C. Consequently, thin lines of lifted photoresist, visible under an optical microscope, either contaminate the chamber wall with fragmented resist or slowly clot the throttle valve in the exhaust line. This problem leads to increased process residues and has an adverse impact on productivity because of the need for more system maintenance. Oxide loss is always a concern when fluorine-based gas is added to standard oxygen plasma resist removal. The degree of oxide loss not only depends on the process temperature and concentration of fluorine, but also on the plasma generation source, be it a line-of-sight RF or downstream microwave source. Recent investigation of microwave-powered downstream plasma has demonstrated that oxide loss can be kept as low as 5 Å/min with careful monitoring of the percentage of fluorine species. However, even this level of oxide loss may not be acceptable for certain advanced devices with ultrathin gates. Wafer Damage According to VLSI Research, minimizing wafer damage is a key initiative for manufacturers that are developing semiconductor equipment for advanced processes. Plasma-induced damage is well understood, and the use of downstream microwave plasma has been thoroughly documented as the optimal plasma source to prevent detectable device damage (see Table I). The addition of a Faraday cage can help minimize damage using RF plasma by trapping charged species, but the additional risk of metal contamination is unacceptable. Potential damage incurred during the residue removal process can be avoided with new, application-specific technologies. These include fluorine-based processes used in conjunction with careful monitoring and adjustments of results through SEM residue analysis and damage evaluation methods such as CHARM, CV shift, and antenna structures.
Table I: Device damage comparison of RF versus microwave plasma sources. Fab Productivity The demands on fab productivity are advancing as quickly as those on technology. Long process times and yield-limiting residues are unacceptable elements in typical implanted resist removal. To keep up with productivity demands, throughput must be increased. Another factor affecting productivity is the addition of wet residue removal processes, which has a significant impact on the amount of process equipment in the fab. More importantly, such tools increase the number of steps required to process a wafer, making manufacturing more complicated, cumbersome, and costly. Device-Specific Trends A number of trends in IC manufacturing summarized below promise to increase the challenges facing the industry. As implant voltages and current increase and as new materials and technology demands are adapted, the resist skin thickens and contains increasing amounts of solvent. Larger dosages will densify the skin, making resist removal without popping even more problematic. This results in longer process times and hampered productivity. Resist coverage will increase on some of the high-dose implant levels in the fabrication process as the active-area sizes decrease. This will also add to the severity of the popping problem. Device geometries will shrink with thinner oxides, making device damage an ever more critical issue. The higher currents necessary for improved throughput will also increase oxide sputtering, which requires a fluorinated postresist removal clean, thus increasing oxide loss. Delays between implant and resist removal further complicate residue removal. Over time, absorbed moisture increases the tendency of resist to pop along the wafer edges. New resist materials will change the general process requirements as well as skin composition and characteristics. All these factors will create significant technical and economic hurdles for the IC industry as technology enters the sub-0.25-µm generations. Technology Roadmap Considerations The energy applications required to support the next three CMOS technology nodes (0.25, 0.18, and 0.15 µm) in ion implantation have migrated to the ultralow and ultrahigh ends of the spectrum. Table II presents the technology roadmap data as adapted from the 1997 revision of The National Technology Roadmap for Semiconductors. Shrinking geometries lead to decreases in gate oxide thickness, junction depth, and thermal budgets. Scaled-down CMOS design rules require the reduction of junction depths to <100 nm of the p+/n and n+/p source and drain junctions, in order to suppress short channel effects. These junctions must also have low sheet resistance in order to maintain high currents and correspondingly high device speeds. High dose implants (1—4 x 1015 atoms/cm2) at very low energy (1—30 keV) are critical to form the drain extensions and to achieve low junction leakage currents at the 0.25-µm technology node. The industry expects the energy levels to decrease to 2—3 keV for the 0.18-µm node.
Table II: Excerpts of the SIA roadmap showing trends in ion implantation. The integrity of gate oxides will become increasingly difficult to maintain as their thickness is scaled down to <40 Å. Charge and contaminants induce damage to the oxide and affect the gate oxide's ability to prevent dopant diffusion between the gate and channel regions of the device. Polysilicon doping requires precise tailoring of dopant depth profiles of the n+ and p+ polysilicon gates. High-dose implant (8 x 1015 to 2 x 1016 atoms/cm2) at very low energy levels (10—30 keV), coupled with careful control of subsequent thermal processing, minimizes dopant diffusion into the channel regions. Moreover, high beam currents are used to enhance wafer throughput. Charge buildup during resist removal must be minimized, in order to prevent gate oxide voltages from exceeding the breakdown limit. High-Energy Implantation High-energy implantation enables the fabrication of more- sophisticated, higher-performance device structures while reducing process complexity and cost. High-energy systems are used in many applications, including retrograde well structures and high-dose buried layers. Trends for each of these applications are presented below. Retrograde twin wells implanted after field isolation (LOCOS or shallow trench) have become standard for sub-0.25-µm technologies because they help to simplify the process (fewer mask levels and lower thermal budget) and improve isolation performance (latch-up control, punch-through suppression, and soft-error reduction in DRAMs). This application needs up to 1-MeV energy at doses of 1 x 1013 to 5 x 1013 atoms/cm2. Retrograde triple wells, rapidly being implemented across all CMOS technologies, improve isolation from substrate noise and permit optimization of devices used for different applications on the same chip. Triple-well applications require energies up to 4 MeV at doses of 1 x 1013 to 3 x 1013 atoms/cm2. About 90% of the devices are designed with twin wells at the 16-Mb generation; however, about 70% of the 64-Mb DRAM designs use triple wells. The transition to retrograde twin and triple wells from diffused twin- and triple-well structures eliminates two mask layers and high-temperature well drive-ins. These are some of the major reasons that high-energy ion implant systems are one of the fastest growing sectors of the semiconductor process equipment business. High-energy, high-dose buried layers represent another emerging trend in high-energy applications. The buried layers can significantly improve latch-up immunity as well as the gettering capability—for both metals and oxygen—of bulk wafers, providing an alternative to expensive epitaxial wafers. These layers require energy levels up to 2 MeV and doses up to 1 x 1015 atoms/cm2. With these trends in high-energy applications comes a trend in resist removal complexity. Resist outgassing, a major production issue, increases linearly with beam current and energy—the use of high-dose implants results in a carbonized crust on the resist. Traditional removal methods are not viable in today's demanding production environment, and alternative solutions are needed to keep pace with productivity and device reliability. Traditional Solutions There are two traditional approaches for the removal of implanted Novalak resin photoresists. This commonly used resist begins to bubble above 120°C. Since crust layers are getting thicker and process times of typical damage- and residue-free processes are getting longer, efficient residue removal affects productivity more directly than ever. The first approach blasts off the resist with intentional popping and follows it with a Piranha or other wet clean. This method requires frequent preventive maintenance and weekly chamber cleaning to meet particulate specifications. Moreover, this approach becomes less effective as device geometries continue to shrink and the crust becomes thick, dense, and difficult to remove. The large resist flakes and implant residues caused by very high temperatures can remain on the device and are not always removed by a wet clean (see Figure 6). High-dose implant resist (>1 x 1015 atoms/cm2) can explode at elevated temperatures. Data from equipment with dual-chamber microwave downstream plasma chambers, equipped with closed-loop temperature-controlled (CLTC) platen and lamp control, have shown that it can remove most high-dose implant resist with minimal popping and residues (PEP3510A, GaSonics International, San Jose). Such tools feature programmable platen temperature, which combines wafer lifting up or down for precise control of a multistep recipe for different temperature levels. A low-temperature step allows controlled removal of the carbonized layer with minimal resist popping; a high-ash-rate step follows to remove the bulk resist at elevated temperatures. Finally, forming gas is used to assist in the complete removal of arsenic and any other remaining residue. A dual end-point detector (EPD) specifically designed for high-dose implanted resist removal detects the end of the carbonized layer removal process with rising signal detection. It also detects the end of the bulk resist process by using falling signal detection. The EPD's accuracy reduces the process time by eliminating unnecessary overash in multiple steps, improving throughput significantly. Figure 7 shows a typical EPD curve. To ensure total residue removal for heavy implanted resist, a sulfuric/peroxide treatment is commonly used as a post—wet clean.
Because of the aforementioned trends in implant dose and energy, unvolatiled oxide residue from ion sputtering during resist implantation forms along the chamber sidewall or resist layer. This layer remains on the wafer after the complete removal of bulk resist and implant residues. As seen under a SEM, these residues are not removed with oxygen and forming gas. Bleeding small amounts of fluorine (<8%) with oxygen will help eliminate the unwanted residues. However, some oxide loss occurs with fluorine chemistry; a four-full-factorial designed experiment (pressure, oxygen, CF4, and forming gas) performed in the resist removal tool investigated keeping the oxide loss to a minimum of <10 Å/min (see Figure 8). There are, however, some advanced implant applications (dual-dopant, high dose/high energy) where the addition of fluorine in the tool does not completely clean the wafer and additional wet cleaning is required. The addition of even higher flow rates of fluorine will push the oxide loss to unacceptable levels as well as increase the wear rate of the quartz plasma generation tube.
Advanced Solutions Advanced semiconductor processing requires the removal of high-dose implanted photoresist at high throughput and low cost, with no residue or damage and minimal or no oxide loss. Lowering the temperature to well below the photoresist bake temperature (115°—120°C) is the key to successfully removing the dense carbonized layer without resist popping and any residue remaining. However, ashing the resist at low temperature leads to a slower ash rate, long process time, and lower throughput. As mentioned earlier, the implant process damages the resist, causing some carbon-hydrogen bonds to release hydrogen and form carbon-carbon bonds, which creates a cross-linked amorphous carbon compound with a graphitelike structure. The solution—breaking these bonds with a soft directional ion bombardment—allows the process to remove the high-dose implanted resist at a very low temperature with high ash rate and very short process time. A new downstream plasma source uses proprietary technology that combines RF and microwave downstream plasma (Directional Downstream Plasma, GaSonics). Using this source, the user can add small amounts of ions to the plasma to accelerate crust removal at low temperatures. The high-dose implant resist crust is quickly removed (<<30 seconds) at a low temperature (50°—70°C) without resist popping and minimal damage from charge buildup. The plasma is generated using low oxygen flow at low pressure (200—400 mtorr) and low RF power. The removal rate is very high (>7000 Å/min) with 3—4% (1x) uniformity. The use of two plasma source technologies separates the production of low-density ions in the soft RF plasma from the generation of highly concentrated reactive neutrals in the high-density microwave plasma. The resulting high rates and low damage can facilitate the formerly difficult removal of dense, refractory materials without any physical enhancement. The independent power sources also allow the direct measurement of the direct-current bias applied to the wafer, permitting direct control of potential damage. Tests were run on wafers that provided the most challenging production conditions. Doses and energy levels of arsenic, boron, and phosphorous varying from 5 x 1015 to 1.6 x 1016 atoms/cm2 and 40 to 100 keV, respectively, were implanted on 200-mm wafers with 1.2 µm of nonpatterned photoresist (Shipley 1811, Shipley, Marlborough, MA). The wafers processed using the plasma source demonstrated excellent results. Nonpatterned wafers are not only challenging to process because of the lack of open area to exhaust solvent, but they clearly show minute amounts of popping. As shown in Figure 9, no popping or residues were observed on test wafers under the microscope's dark field.
Running similar processes on patterned wafers yielded equally impressive results. Figures 10 and 11 reveal the process to be residue free, requiring only a deionized-water rinse after the plasma process. In addition to the results on the wafer, the tool platform comes with a buffering station that allows stacking of up to six cassettes, which can significantly improve the utilization of the system and OEE. To maintain high throughput on a system with only two cassettes commands a high level of operator attention. This potential bottleneck is significantly reduced with the buffering station, which has further implications for the implant area not discussed here.
Conclusion As devices shrink, higher implant doses and energies will continue to thicken the hard crust and increase the difficulty of removing resists. High-volume, advanced IC manufacturing requires a damage- and residue-free process that eliminates heavily implanted photoresist with minimal oxide loss. This is another example of how advances in wafer processing must evolve to meet the demands of device technologies and manufacturing efficiencies. Acknowledgments The authors would like to thank John Rembetski and Woody Chung of GaSonics International for their valuable input. Their extensive knowledge of implanted resist removal and process engineering experience has been instrumental in developing the new downstream plasma source. Bibliography Hirose K, Shimada H, Shimomura S, et al., "Ion-Implanted Photoresist and Damage-Free Stripping," Journal of the Electrochemical Society, 141:192, January 1994. McOmber J, and Nair RS, Nuclear Instruments and Methods in Physics, B55:281, 1991. McOmber J, Ostrowski K, Meloni M, et al., Nuclear Instruments and Methods in Physics, B74:266, 1993. McOmber J, Ostrowski K, Whitney L, et al., "An Integrated Resist/Implant/Ash Study of Different Photoresists," in Proceedings from the 10th Ion Implantation Technology Conference, Elsevier Publishers (The Netherlands), June 1994. Rubin L, and Morris W, "High-Energy Ion Implanters and Applications Take Off," Semiconductor International, 20(4):77, 1997. The National Technology Roadmap for Semiconductors, San Jose, SIA, 1997. Andy Kirkpatrick is the director of product marketing and customer technology for GaSonics International (San Jose). Before joining the company in 1996, Andy held various marketing, technical support, and operations positions at Applied Materials. He earned a BS in mechanical engineering from the U.S. Naval Academy (Annapolis, MD) and is a U.S. government—qualified nuclear engineer. He also received an MBA from University of California, Berkeley's Haas School of Business. (Kirkpatrick can be reached at 408/570-7193 or andrew_kirkpatrick@gasonics.com.) Neil Fernandes is director of customer technology for GaSonics, where he has been employed since 1997. He previously worked at Watkins-Johnson, where he was the manager of the applications lab, responsible for the design, build, and start-up of the lab and W-J's "Samples for Success" program. Fernandes holds an MS in mechanical engineering from the University of Texas at Austin and is an active member of the Electrochemical Society. Tinal Uk is a senior applications engineer at GaSonics International. He joined the company in 1986 as a technical specialist working jointly with customers on developing solutions for photoresist removal. Since 1990, he has been an applications engineer working in process development of photoresist removal, isotropic etch, and postetch residue removal. He has authored two papers on ash and clean applications. Gary Patrizi is a technology development engineer at Philips Semiconductors in Albuquerque, NM. He is responsible for front-end etch development. Before joining Philips in 1996, he was a process development engineer in the Compound Semiconductor Research Laboratory at Sandia National Laboratories. There he worked to develop heterojunction bipolar integrated circuit processes. He holds BS and MS degrees in electrical engineering from Colorado State University (Fort Collins, CO).
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Figure 1: Implanted resist has a carbonized skin layer and trapped solvent. Escaping solvent is represented by outgoing arrows.
Figure 2: The transition from crust to bulk resist removal is evident from the distinct change in removal rate for various process temperatures.
Figure 3: SEM photo of resist residues from popping.
Figure 4: Resist removal is pattern dependent and most problematic along the edge and in unpatterned areas.
Figure 5: Oxide forms along pattern sidewalls from sputtering caused by ion flux (a); sputtered oxide residues left after resist removal (b).
Figure 6: Residues as seen by darkfield inspection.
Figure 7: Typical end-point trace for crust removal.
Figure 8: Oxide loss control with CF4, where constant parameters are 130°C, 1300 mtorr, O2 = 1000 std cm3/min, FG = 400 std cm3/min, and time = 60 seconds.
Figure 9: A low-temperature 50°C process with a 20-second crust removal step yields excellent results (top); an additional 10 seconds of crust removal yield a residue-free water (bottom).
Figure 10: Processed patterned wafer before DI rinse (top); after DI rinse the wafer is residue free (bottom).
Figure 11: A large residue flake (top) from incomplete dry resist removal that, if not removed in a subsequent wet process, will cause device failure; and (bottom) residue-free process without a subsequent wet clean.