MAPPING THE ROADMAP

Assessing future technology requirements for rapid isolation and sourcing of faults

Charles Gross, Intel; Kenneth W. Tobin, Oak Ridge National Laboratory; David Jensen, Sematech/AMD; and Dinesh Mehta, Semiconductor Research Corp.

(Fourth in a series)

Fewer defects than ever before are being found on wafers in state-of-the-art manufacturing fabs. Improved detection methods and tools have enabled the identification of killer defects closer to their source, and improvements made by process tool suppliers have reduced defect densities at every process step. This has led to quicker yield ramps and higher yields on increasingly complex circuits. It has not, however, reduced the challenges of isolating the defects that cause electrical failures on these circuits which are found at parametric test and at sort. These challenges will grow as the killer defect sizes shrink, the number of process steps and circuit elements increase, and management comes to expect higher yields on larger circuits. The defect sources and mechanisms subgroup of the defect reduction (DR) Crosscut Technology Working Group (CCTWG) was formed to address this concern and propose potential solutions in the latest revision of The National Technology Roadmap for Semiconductors (NTRS).1 This subgroup comprised experts from semiconductor manufacturers, industry consortia, equipment suppliers, academia, and national laboratories.

The following model can be used to explain the working relationship among the various DR CCTWG subgroups. The defect prevention and elimination subgroup shows how to prevent as many defects as possible from getting onto the wafer surface. Defect detection tells how to find those defects that penetrate the fab's defenses. Yield modeling and defect budgeting predicts the impact of defects throughout the process on circuit yield. Defect sources and mechanisms describes potential methods to isolate and quickly find the root causes of the defects that survive the process and can have an electrical impact on the circuit. This latest installment in the Mapping the Roadmap series focuses on fault isolation techniques and the integrated yield management system necessary to analyze the diverse data sets and to make the correlations necessary to assign root causes to defect sources.

The Challenge

Fault isolation in current and future technology generations presents a difficult challenge today and an orders-of-magnitude more-difficult challenge after the turn of the century. As Figure 1 shows, the NTRS predicts that for microprocessors, the number of process steps will increase nearly linearly, and the number of transistors in a circuit will increase exponentially from one process generation to the next.1 Accordingly, as minimum feature size decreases from one generation to the next, killer defect size (or critical size, defined as one-half the minimum feature size) decreases proportionately. To achieve a 60% yield target on a complex microprocessor in its first year of manufacturing, defect density must also decrease from one generation to the next. Figure 2 depicts the predicted defectivity reduction.

Figure 1: Predicted complexity growth for microprocessors.

Figure 2: Predicted defectivity reduction for microprocessors.

The challenge is to isolate a shrinking needle in a growing haystack. The needle is a killer defect, whose size decreases over time. The haystack is a chip with a constantly expanding volume, within which the number of circuit elements grows exponentially. The fault isolation volume, which is defined as the product of the number of process steps and the number of transistors, represents the space that an electrical fault must be isolated within in order to assign a root cause. Figure 3 illustrates the challenge by graphically depicting how quickly the needle shrinks and the haystack expands. When we compute the ratio of the haystack (fault isolation volume) to the needle (critical size in nanometers) in the 250-nm generation, it is on the order of 108:1. By the 150-nm generation, the ratio will grow tenfold, to 109:1. By the 50-nm generation, the challenge increases another thousandfold to 1012:1. The industry's challenge is clear: we must work together to continually improve design, manufacturing, test, and failure analysis resources at a fast enough pace to overcome this exponentially escalating problem.

Figure 3: The challenge of finding ever-smaller killer defects in the milieu of constantly expanding chip volumes.

Fault Isolation

From the yield learning perspective, fault isolation is a necessary element of the failure analysis methods that provide the yield engineer with defect sourcing information. Such isolation is typically accomplished by zeroing in on the defect location and deprocessing the circuit; that is, by destructively removing layers to determine which manufacturing step introduced the problem. The ability to localize these defects at future technology nodes represents a major challenge to the rapid determination of existing yield-limiting conditions. Because of the crosscutting nature of this challenge, solutions must be pursued that encompass new strategies for design and test, improved defect detection, and new yield management methods for determining source mechanisms.

Sub-0.1-µm pattern and particle defects will account for a growing percentage of device faults as critical dimensions shrink below 0.25 µm. These defects will not be readily detectable by optical means, and it will be several years before higher-resolution tools such as scanning electron microscopy (SEM) will be able to perform efficient and rapid whole-wafer analysis. A significant fraction of fault-related events on the wafer already are linked to nonvisible defects resulting from parametric issues. Because of the increased time and expense of manually isolating these faults, the development of automated diagnosis methods and tools becomes critically important. Understanding and correcting failure mechanisms cannot occur unless faults are localized rapidly to an area of the device that can be cost-effectively inspected and a failure mechanism can be assigned.

Special test structures (serpentine patterns, combs, and the like), memory array test chips, and microprocessor memory arrays are employed to monitor manufacturing-induced electrical faults. The test structures are used for locating breaks and shorts. Memory arrays can localize these types of defects and also provide the advantage of detecting gate oxide shorts and related transistor defects. Test structures and memory arrays are productive but do not map well onto the direct detection and localization of faults on nonarrayed devices.

Localizing faults based on electrical test is time-consuming and tedious on logic devices. For these devices, new methods based on design for test (DFT) and built-in self-test (BIST) will be required to facilitate fault localization through test vector signature analysis. The increasing demand for mixed-signal digital and analog devices only exacerbates the problem. Since analog devices can operate in a continuum of electrical states, electrical test signature analysis can be indeterministic. The software design and analysis tools required for DFT, especially for mixed-signal devices, are in their infancy. The voltage contrast scanning electron microscope and other new tools for physical device testing could allow fault isolation within the circuit while requiring limited knowledge of the design. Some combination of physical and electrical test, BIST, and failure-mode modeling must evolve in parallel to address the fault isolation challenge.

Invisible Defect Sourcing

An invisible defect is defined as one that causes an electrical fault and leaves behind no detectable physical remnant. Examples of such defects in current processes include localized parametric variations (resistivity variation, capacitance variation, poly depletion effects), localized poisoning (ionic contamination, crystalline/bonding defects), and localized masking issues (blocked implant or unblocked implants). An invisible defect can also be defined as one too small to be seen with available failure analysis tools.

Invisible defects can be attacked in several ways. Localized parametric, poisoning, or implant masking defects can be prevented. The use of advanced test structures specifically designed to identify these mechanisms early in the process development cycle can help minimize the occurrence of invisible defects on future products. These structures must be devised to quickly isolate the invisible mechanisms at the layers in which they occur. Short- and full-flow test vehicles should be developed expressly for this purpose.

Once a defect causes an electrical fault and that fault is isolated, the defect source may be determined by mapping the fault location to a previously existing in-line defect location. When the defects detected in-line are correlated to electrical failures, this saves time and energy for both invisible and visible defect analyses. Current defect detection tools have coordinate accuracy of ~3000 nm, so correlating the location of a defect on a device with a minimum pitch of 500 nm can be challenging. The NTRS predicts that coordinate accuracy for defect detection equipment will improve to ~1000 nm by the time a minimum pitch of 100 nm is achieved. The art of matching in-line defect sites to failed circuit elements will not get any easier for yield analysts in the years to come.

If no in-line defect is found in the electrical fault area, the next step is to model the failure mechanisms that could cause the type of electrical fault experienced on the circuit and determine via probability analysis what the most likely cause was. This task can be overwhelming on logic circuits, even when 3-D computer-aided design tools are interfaced with failure analysis instrumentation; just determining the number of possible failure locations may be computationally prohibitive. Applying BIST to cache memory sections on the chip can improve the chances for success, especially on chips that have large areas of memory arrays. Another way to improve the probability of correlation to failed die sites is to strengthen the collection of parametric data from the circuit tester (forward-biased pad diode resistances, Iddq, Voh, Vol, Iozl, and the like) so that parametric correlation and analyses may become possible.

Integrated Yield Management

Yield management systems have a fundamental purpose: to collect and store relevant manufacturing information for the yield engineer's use. They provide a historical record of the manufacturing environment for use in yield learning. The system is used to improve yield by monitoring (e.g., yield at sort), linking yield loss to defects and parametric data, and ultimately linking defect and parametric data to processes and tools. The goal is to rapidly learn about and locate errant fabrication processes so that they can be shut down, serviced, and corrected. Historical yield data also provide a link between past processes and the design of new process methods, an important consideration in the rapid ramp-up required by fabricators in today's competitive market. Figure 4, for example, shows a dramatic reduction in the time to maturity for DRAM devices, ranging from roughly 5 years for 64-Kb DRAMs to approximately 1 year for 64-Mb DRAMs.

Figure 4: Current trend in reduced time to maturity for DRAM production. (Source: VLSI Research)

The roadmap describes the challenge associated with integrated yield analysis capabilities in terms of the need "to develop 'smart' software tools that quickly and automatically access multiple databases and establish correlations between data of different types. Some data sources will be time based, others will be wafer based, still others will be chip based. On-wafer coordinates must be unified and data formats must be standardized. Automatic data reduction algorithms to source defects from multiple data sources must be developed to reduce defect sourcing time."1 Table I shows current manufacturing complexity trends along with the paradoxical need to reduce the time required to source manufacturing problems and recognize preexcursion trends in the data. A reduction in the time required to source fabrication problems and recognize trends from weeks to days to hours will be necessary if reduced time-to-maturity goals are to be achieved.

Table I: Defect sources and mechanisms technology requirements.

To address this challenge, there must be new technologies that can automatically detect yield-impacting events during device fabrication. The trend over the past several years has been to develop analysis tools that can assist yield engineers by automating tedious manual inspection jobs, therefore making more of their time available for other important tasks. Technologies such as automatic defect classification (ADC), spatial signature analysis (SSA), and defect-based statistical process control (SPC) are time-saving tools. ADC provides an automatic classification of in-line and off-line optical and SEM defects.2 SSA provides automatic recognition of unique process signatures for in-line optical and final electrical test bin-map data.3, 4 A spatial signature is a unique distribution of wafer defects originating from a single manufacturing problem that is indicative of its source. Automatic recognition of unique spatial signatures can quickly guide the yield engineer to the source of the manufacturing problem, while ADC can rapidly reveal specific details associated with particle and pattern problems. Both of these techniques working together have a positive impact on the time-to-discovery process.

Defect-level SPC historically has been associated with monitoring whole-wafer defect counts. SSA and ADC information adds context to the wafer defect data and allows for a higher resolution of information to be monitored. Instead of simply counting particles from lot to lot, a statistical estimate can be made of the random and systematic components of a defect distribution, e.g., how much scratching is occurring, how many tungsten particles there are, or how many random particles are being generated from process equipment (versus systematic distributions). Figure 5 schematically shows these concepts in the yield management environment.

Figure 5: Schematic representation of yield management in a fab showing the insertion of automation technologies to assist the yield engineer.

While the level of automation associated with SPC, ADC, and SSA is providing new and efficient data reduction capabilities, these tools primarily comprehend product data only. As represented in Figure 5, most fabrication facilities maintain only a loose coupling between their process, product, and wafer-in-process (WIP) database systems. The ability to maintain and correlate time-dependent process data (tool health data, in situ sensors) with product data (wafer maps, bin maps, discrete defect types) is only beginning to evolve.

To source manufacturing problems more quickly, all available data sources must be used to pinpoint the system or systems that cause each problem.5 The ability to detect changes in process equipment over time—temporal analysis—requires merging product and process databases. Temporal analysis will include time-based sensors coupled with the additional data context provided by high-resolution SPC, ADC, and SSA.6 These data sources from various points in the process will have to be integrated to achieve a truly automated understanding of product yield issues. The ability to integrate off-line inspection tool data (SEM, energy-dispersive spectroscopy, Auger, atomic force microscopy, time-of-flight secondary ion mass spectroscopy, transmission electron microscopy, and the like) into a rapid sourcing analysis environment also will be necessary to understand the elemental composition of various contamination sources and their deposition mechanisms.7 This technology's architecture is in its infancy and requires continued support on an industrywide level in order to achieve future productivity goals.

Conclusion

Fault isolation in future technology generations will become increasingly difficult. For complex logic devices, fault isolation techniques must be designed into complex circuits. Process development must ensure that all types of defects are controlled and characterized early on, and defect detection tools used in manufacturing must have optimum detection and coordinate accuracy capabilities. Failure analysis tools must evolve to meet their detection capability roadmap. Yield analysts must have access to a fully integrated analysis system that seamlessly interfaces to wafer-based, chip-based, transistor-based, and in-line time-based data sets. Test programs must have the capability to generate fault isolation data and save key parametric information. Once all of these functions work together to attack fault isolation and defect sourcing problems, achieving high yields in an exponentially more complicated world will be possible.

Acknowledgments

Portions of this article are adapted from The National Technology Roadmap for Semiconductors 1997 revision. Used with permission. The authors also want to acknowledge the following DR CCTWG participants: Milt Godwin, Robert Alexander, Wojciech Maly, Hank Walker, William Fil, Terry Francis, and Tom Bzik.

References

1. The National Technology Roadmap for Semiconductors, San Jose, SIA, 1997.

2. Bennett MH, Tobin KW, and Gleason SS, "Automatic Defect Classification: Status and Industry Trends," Integrated Circuit Metrology, Inspection, and Process Control IX, Santa Clara, CA, SPIE, vol 2439:210—220, May 1995.

3. Tobin KW, Gleason SS, Karnowski TP, et al., "Automatic Classification of Spatial Signatures on Semiconductor Wafermaps," Metrology, Inspection, and Process Control for Microlithography XI, Santa Clara, CA, SPIE, vol 3050:434—444, July 1997.

4. Gleason SS, Tobin KW, and Karnowski TP, "Rapid Yield Learning through Optical Defect and Electrical Test Analysis," presented at Metrology, Inspection, and Process Control for Microlithography XII session at SPIE's 23rd International Symposium on Microlithography, Santa Clara, CA, February 1998.

5. Tobin KW, Gleason SS, Lakhani F, and Bennett MH, "Automated Analysis for Rapid Defect Sourcing and Yield Learning," Future Fab International, 1(4):313, 1997.

6. Butler SW, Hosch J, Diebold AC, and Van Eck B, "Sensor- Based Process and Tool Control," Future Fab International, 1(2):315—321, 1997.

7. Diebold AC, Uritsky Y, Brundle D, et al., "Understanding the Physical Metrology Needs for Ultra Clean Manufacture of Future Silicon Integrated Circuits," Future Fab International, 1(1):227—235, 1997.

Charles Gross is yield analysis group leader at Intel's Fab 17 (formerly Digital's Fab 6) in Hudson, MA. He was formerly senior engineering manager of Digital Semiconductor's yield engineering group. Gross joined Digital's semiconductor organization in 1987, and his responsibilities there included engineering management in wafer fabrication and yield engineering. He also served as Fab 6 program manager from conception through start-up of the facility. Before joining Digital, Gross worked for RCA and Commodore Semiconductor. He has a BS in physics from Drexel University. (Gross can be reached at charles.gross@intel.com.)

Kenneth W. Tobin, PhD, leads the Image Science and Machine Vision Group at Oak Ridge National Laboratory (ORNL), Oak Ridge, TN. His technical research includes scene analysis and pattern recognition for machine vision as applied to industrial real-time, high-speed inspection, and automation problems. He has been doing research with the semiconductor industry since 1991, performing R&D for optical image defect classification and electronic wafer-map spatial signature analysis and data reduction. He has authored or coauthored more than 50 technical publications in the areas of nondestructive test and analysis, signal and image processing, and pattern recognition. Tobin is a member of the Optical Society of America and the International Society for Optical Engineering (SPIE), where he is a cochairman for the SPIE Conference on Machine Vision Applications in Industrial Inspection. He is also a member of the Defect Reduction Crosscut Technology Working Group for SIA's National Technology Roadmap for Semiconductors. He has a BS in physics and an MS in nuclear engineering from Virginia Polytechnic Institute (Blacksburg) as well as a PhD in nuclear engineering from the University of Virginia (Charlottesville). (Tobin can be reached at 423/574-8521.)

David Jensen is program manager for defect reduction technology at Sematech, Austin, TX. He is an Advanced Micro Devices assignee and while there, as a member of the technical staff, his primary responsibilities were development and deployment of contamination-free manufacturing strategies. Before joining AMD, Jensen was at Digital Semiconductor for five years, where he was engineering supervisor of the Fab 6 CFM group. He served as cochair of the DR CCTWG for the 1997 revision of the SIA NTRS. He has also worked extensively in the semiconductor process equipment industry for ASM America and Spectrum CVD, holding numerous positions in design and engineering with emphasis on contamination control in process equipment. He has written numerous papers and has presented widely on contamination control and defect reduction technology. Jensen holds a BS in mechanical engineering from Arizona State University (Tempe). (Jensen can be reached at 512/356-3756 or david.jensen@sematech.org.)

Dinesh Mehta, PhD, is vp of administrative operations and strategic initiatives and a member of the office of the chief executive at the Semiconductor Research Corp., Research Triangle Park, NC. He came to SRC in 1996 after a long career at AT&T, where he held senior executive—level assignments in R&D, engineering, manufacturing, and product management. He has BE and MS degrees in mechanical engineering and MS and PhD degrees in material science. (Mehta can be reached at 919/941-9435 or mehta@src.org.)

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