VIEWPOINT

Automated defect inspection: Facing the challenges of decreasing critical dimensions, new processes, high aspect ratios

(First of two parts)

Paul Sandland

There is no fundamental physical reason why defect inspection sensitivity, speed, and classification cannot keep pace with the steadily increasing complexity of manufacturing integrated circuits at high yields. Although cost is a critical issue, if we understand the defect generation process well enough to look for the right problems in the right places at the right times, the volume of data decreases and the cost of inspection can be contained. A thorough, systematic, and unbiased review of each aspect of the fabrication process is needed to determine how inspection can best be implemented. Having the right equipment is not enough. There must also be knowledgeable team members whose understanding of the best practices of semiconductor manufacturing and intimate familiarity with the utilization of inspection equipment help the customer to use those tools effectively. Within this context, here are some key challenges that lie ahead in automated defect inspection.

Decreasing Critical Dimensions

As critical dimensions shrink from 0.25 to 0.13 µm over the next five years, inspection tool manufacturers face challenges in extending the life of their current yield enhancement tools. Advanced manufacturing linewidths on reticles should decrease from 1.75 µm (0.35 5x reticles) to 1.0 µm (0.25 4x reticles) this year alone. Some wafer defects as small as one-third of the design rule can cause yield failures within the process. Defects as small as 50 nm will soon have to be detected to meet the needs of advanced yield analysis engineering work. Not only must equipment vendors make evolutionary changes to current inspection tools, they must also develop new revolutionary detection techniques to meet these requirements.

Optical inspection systems are limited by their resolution. While one cannot physically separate size and brightness for a 100-nm defect using any practical ultraviolet or visible optical system, defects of this size and smaller can still be detected with visible light. In practice, however, such sensitivity is possible only on an early level, or for particles on a planar surface where noise sources are limited. Noisy surfaces—such as grainy metal, where yield loss may be acute—will be problematic. One solution might be at hand: the copper chemical mechanical planarization (CMP) interconnect process may be grain free and thus inspectable with optical tools.

SEM voltage contrast imaging can detect electrical defects below the resolution of current optical systems. Shown here are two interconnect defects, one a poorly formed contact to substrate (top), the other a void in a previous contact layer (bottom).

Low-voltage scanning electron beam (E-beam) inspection has several advantages over optical inspection. Bridges between metal lines and many other defects alter the capacitance of a given structure on the wafer. This change can be detected through the use of voltage-contrast imaging; the accompanying figure shows two examples of defects found using this technique. Fatal defects below the resolution of current optical systems can now be detected using voltage contrast with the same pixel sizes used in a visible light optical inspection system. In fact, voltage contrast imaging may be the only viable inspection solution for a large number of interface defects that exist within the interconnect process (contact, via, metal) that can cause reliability, performance, or yield failures. E-beam systems can also find small defects that are undetectable by bright- or darkfield light optical systems and that do not produce voltage contrast signatures, although more resolution is needed and slower inspection throughput is the result. Several of these systems in routine use provide a new method of defect detection for classes of fatal defects that cannot be found by other means. Low-voltage E-beams, however, usually cannot detect defects below or in thick insulating layers, although optical systems often can. Optical and E-beam systems will therefore continue to coexist because of their inherently different detection mechanisms.

New Equipment, Materials, and Processes

Photolithographic equipment manufacturers face tremendous challenges in developing solutions (material, process, and imaging) for advanced processes at state-of-the-art design rules. As a result, more attention is being paid to defects discovered after the photoresist has been developed. Postdevelop inspections have typically been performed manually by technicians on a microscope, inspecting for gross, easily identifiable process and defect anomalies. There is, however, a growing realization that manual inspection is no longer cost-effective, and automatic defect inspection at this step will pay for itself in improved yields. A useful subset of photolithographic defects can be detected with relatively large pixel sizes using a high-speed inspection system at relatively low cost. The use of several of these specialized inspection tools, coupled with high-sensitivity sampled inspections, should provide tremendous leverage for improving yields more quickly within the photolithography process.

Novel materials will be required as the industry approaches 100-nm minimum design rules, including new gate dielectrics and gate electrodes to replace thermal silicon oxide and polysilicon. Along with the move to copper interconnects, low-k dielectric interlayer materials will be needed to reduce gate and signal propagation delays without increasing the number of metal layers. The processing of these new materials will likely be more difficult and will produce new defect types and process noise. The inspection equipment industry must provide solutions to overcome these issues if yield progression is to continue.

Copper dual-damascene processing is perhaps the most challenging new development. Driven by logic chipmakers, dual damascene will increase device performance (due to better electromigration properties) while lowering manufacturing costs (by reducing the number of processing steps). One of the main advantages of damascene processing is that it eliminates the need for metal etch. This is critical to the industry's planned move from aluminum to copper, since copper is difficult to etch. While the elimination of metal etch will eliminate many critical defect types that can have a serious impact on yield, the use of a dual-damascene process will introduce new defect types. In addition to high-aspect-ratio interface defects, there will be new defect types and yield issues associated with new materials (low-k dielectrics, copper metal, materials used for copper barrier), processing techniques, and equipment used for this process. The challenge for the inspection and yield management community will be to provide timely identification of the causes of yield loss, preferably singling out a particular process or piece of equipment in need of adjustment.

High-Aspect-Ratio Inspections

A major gap exists between market requirements and tool performance in the area of high-aspect-ratio inspections (contact, via, and metal trench) for production, making this one of the greatest challenges in the years ahead. With aspect ratios of 8:1 for some processes and minimum design rules of <0.25 µm, detecting defects at the bottom of via holes has become increasingly difficult, except by using slow voltage-contrast scanning electron microscopy (SEM) imaging. In addition, noise from color variations and metal grain can result in the capture of noncritical, or nuisance, defects.

The insertion of dual damascene into the process flow poses a series of major concerns for the users of traditional inspection systems. In addition to such postmetal inspection challenges as background noise and decreasing design rules, high-aspect-ratio defects will push optical and laser scattering inspection systems to their limits. With the elimination of metal etch and its resultant defects, critical yield-limiting defects will likely center around those found at interfaces and within the metal substrates, since this new process is similar to the single-damascene process used for tungsten plug processing. In the via tungsten plug process, the top yield-limiting defects arise at the via and metal interfaces (residues, incomplete etch) and within the plug itself (voids, fractures, and other structural issues).

Effective inspection at three key processing points within the dual-damascene process will become essential for the achievement of acceptable yields. Photolithography for via and conductor layers, via and conductor channel etch steps, and soft metal CMP will most likely be the steps giving the greatest yield loss.

Acknowledgments

This article was adapted from a presentation titled "Automated Defect Inspection: Past, Present, and Future," originally presented at SPIE Microlithography, Santa Clara, CA, February 1998. The author would like to thank Robert Cappel of KLA-Tencor's marketing department for his help in preparing this paper. (The second part of this article, which discusses future trends in automated defect inspection, will appear in an upcoming issue.)

Paul Sandland is a senior technical adviser for KLA-Tencor Corp., San Jose. Since joining KLA in 1976, he has been instrumental in the conception, design, and development of numerous inspection technologies. He holds five patents, has written many articles and papers, and has been the recipient of several industry honors and awards.

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