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MAPPING THE ROADMAPWhat drives defect detection technology?Charles Weber, Hewlett-Packard/Sematech; David Jensen, AMD/Sematech; and E. Dan Hirleman, Arizona State University (Third in a series) Defect detection is considered a critical component of the defect reduction cycle. This motivated the defect reduction technology subgroup of the Crosscut Technology Working Group, which helped formulate the revision of The National Technology Roadmap for Semiconductors (NTRS),1 to form its own subgroup dedicated to this subject. Defects are considered events that lead to or can lead to electrical faults in microelectronic circuitry. Their detection requires extensive use of in-line inspection tools, in situ sensors, and electrical testing and failure analysis equipment. Inspection equipment identifies many defects by registering physically detectable anomalies on the wafer surface. In situ sensors detect potential sources of electrical faults in real time and provide important information regarding defect sourcing and generation mechanisms. However, some defects leave no physical trace and must be detected electrically at the end of the line. Failure analysis equipment can then investigate the nature of the defect and identify its source.1—3 Three factors drive defect detection technology requirements in the late 1990s: the shrinking feature sizes of integrated circuits mandate sensitivity to smaller defects; throughput requirements increase as semiconductor processes mature (i.e., more area must be scanned in order to detect statistically significant levels of defects); and more-rapid yield learning requires shorter cycles of learning (defined as the time required to plan an experiment, fabricate the required wafers, test or inspect the wafers, and analyze the data). As the roadmap notes, these factors are at the root of the major challenges now being faced by suppliers of defect detection technology and semiconductor manufacturers. Shrinking Feature Sizes IC feature sizes have been shrinking for more than 30 years, a trend the NTRS expects to continue.4,5 Since circuits with smaller feature sizes are susceptible to electrical faults induced by smaller defects, defect detection technology must become increasingly more sensitive. Suppliers of defect detection equipment continually improve their technology to keep up with these requirements. For example, optically based defect inspection tools feature new light sources with shorter wavelengths and optimize the lens optics for the new physical conditions. This trend should continue until inspection equipment may need to capture defects so small that optically based detection will no longer be suitable for the job. As IC feature sizes shrink, semiconductor processes become more complex, and new defect classes become yield limiters. Figure 1 depicts the systematic failure modes of copper dual damascene, the anticipated choice of global interconnect technology for the 180-nm node. New process technologies like chemical mechanical polishing (CMP) introduce hitherto unknown classes of surface defects,6 while other failure modes reside up to 1500 nm below the surface and are exceedingly difficult to detect. Metal voids and barrier metal punch-through may even elude optical inspection equipment completely.
Figure 1: Systematic failure modes of dual damascene. The increased number of defect types drives up the cost of fault reduction. Since yield engineers have observed that different types of defect inspection equipment capture some defect types more effectively than they do others,7,8 companies are forced to buy many types of defect inspection tools in order to identify most potential sources of electrical faults. As process complexity increases, defect detection may pose a daunting economic challenge to all but the largest semiconductor manufacturers. The Process Life Cycle Process development practices may vary from company to company, but all process development teams face the same physical challenges. In the early stages of research, engineers focus on solving fundamental process problems, relying primarily on in-line metrology and electrical data from microelectronic test structures. Defect inspection becomes increasingly important once VLSI circuits are introduced into the process development effort, when inspection tools detect and identify defects that could be the source of electrical faults. The requirements for these inspection tools change as the process matures and the number of observable defects decreases. The defect detection subgroup defined the following generic phases of the semiconductor process life cycle as they pertain to the evolving requirements of defect inspection.
Figure 2: Chip yield as a function of fault density. Figure 2 tracks the process life cycle through five orders of magnitude of electrical fault density. It also shows why semiconductor process development teams choose different yield vehicles to maximize their yield learning rates during different process development phases. The lower curve in the figure assumes a chip area of 4 cm2, which is anticipated for the node-technology-driving products of the 180-nm process generation. The process R&D phase for such large chips extends down to 0.4 faults/cm2, the yield ramp phase occurs between fault densities of 0.4 and 0.05 faults/cm2, and volume production takes place at <0.05 faults/cm2. The upper curve assumes a chip area of 0.5 cm2. Its yield ramp occurs during the process R&D phase, which makes it an excellent vehicle for fault density estimation at the early stages of the semiconductor process life cycle. Systematic faults and highly clustered defects dominate the process R&D phase, while random defects dominate the yield ramp phase. Thus the Seeds yield model serves as a reasonable approximation for the yield function of fault density estimators, while the Poisson yield model more accurately describes the yield curve of node-technology-driving products.13 Since the objectives of the three phases of the process life cycle are so different, it is not surprising that the technology requirements for defect detection in those phases are different as well, making timing an important facet of a roadmap for defect detection. Each phase of the process development cycle requires specific defect detection tools or recipes, which must be delivered to chip manufacturers just in time. Production release typically occurs when revenue is achieved by manufacturing products associated with the specific technology node (e.g., 250 nm in 1997, 180 nm in 1999), which corresponds to a sort yield of 60%. Inspection tools for process R&D are needed up to four years before the first year of production. Tools that can accelerate the yield ramp must be available about 18 months prior to production release so they can be characterized before the ramp occurs. Volume production generally begins within six months of manufacturing release. Tools that monitor yield excursions in volume production must therefore be available then. It is important to also consider the need for a mix of different tool types, regardless of the yield phase. For instance, specific process tools or modules may be contributing a greater share of yield loss than others, even though overall yield is ramping. In this case, yield ramp—capable defect detection tools and recipes (those with greater sensitivity, slower scan speed) support yield improvement in the low-yielding tool or process, while volume production—capable tools and recipes (those with lesser sensitivity, higher scan speed) monitor the stable tools and processes for excursions. The support of additional products and future process technologies or nodes always requires a certain degree of yield learning, regardless of the ultimate yield plateau. Therefore, yield ramp— and volume production—capable detection tools coexist in most IC fabrication facilities. Because of the combined requirements of shrinking feature sizes and process life cycle, the market for inspection tools is segmented. Shrinking feature sizes drive sensitivity while throughput requirements increase as a process matures. Current inspection tools typically focus on either sensitivity or throughput, with very little latitude for in-line (i.e., in a single tool) trade-off of those performance parameters. This means different tools—-or different recipes on those tools—-are used for different phases of the manufacturing process. IC manufacturers must purchase several kinds of inspection tools, which drives up their process development costs. Clearly, more-agile defect inspection tools would help control industry costs. Shortened Learning Cycles Capital productivity drives the trend toward shorter data cycles. IC manufacturers spend billions of dollars on equipment, and they are interested in obtaining as fast a return on their investment as possible. Rapid yield learning has become an increasingly important source of competitive advantage. The sooner a potentially lucrative circuit ramps to a good yield, the sooner the chipmaker can generate a revenue stream. In addition, the prompt identification of the cause of yield loss during production can restore a revenue stream and prevent the destruction of material in process.14 Recent studies have revealed that shortening the defect learning cycles accelerates yield learning by increasing the experimentation capacity. Defects must be detected, analyzed, and eliminated within increasingly brief time periods. Consequently, successful yield improvement usually consists of a total-systems approach that involves electrical testing, defect inspection, and in situ fault detection. A defect reduction team can thus develop true yield management capability by correlating data obtained from methods with short data cycles to those extracted from methods with longer cycles. Once defect databases become large enough, signals from short-cycle methods can foreshadow effects on final yield.1—3,15—17 Historically, a parametric test stripe placed in the scribe line of an LSI product yielded information on systematic faults once the fabrication cycle was completed. The resulting parametric data complemented fault data and helped engineers debug semiconductor processes.9,12 The learning cycles for this approach essentially equaled the fabrication cycle of a full VLSI process. Some chip firms have improved their learning rates by running complementary short-cycle experiments on test wafers. Their development teams have realized large-area, multipurpose microelectronic test structures by running fractions of the full process in parallel. This approach is very test-wafer intensive but has shortened the cycles of learning of electrical testing by more than a factor of five, localized the source of systematic faults more precisely, and yielded statistically significant random fault density estimates.3,11,18,19 Rapid yield learning now requires cycles that are even shorter than the fabrication cycles of the simplest circuits, making direct electrical fault detection virtually impossible. Fault densities are instead inferred from physical defect counts on patterned product wafers, unpatterned starting material, and test wafers. However, not all defects induce electrical faults that kill circuits. Defect data from inspection and in situ sensors must thus be correlated to functional test data in order to establish kill ratios for specific defect types. Patterned Wafer Inspection IC manufacturers are increasingly relying on in-line data from patterned wafer inspection, which can detect yield-limiting defects with shorter cycles than microelectronic test structures. In-line data provide a cumulative count of defects throughout the process. By subtracting the already-detected defects from the current image, those that have occurred since the previous inspection can be identified and their source can be localized more effectively. In-line inspection of patterned wafers presents defect detection technology with the challenge of position-independent detection, that is, the development of tools that can account for variations in sensitivity or detectability of defects across a product wafer. This is important for two reasons. First, the yield impact of a particular defect will depend on its position relative to the circuit, and second, the apparent size, and hence the apparent significance, of a defect will also depend on position. The signature of defects on patterned wafers illuminated by photon, electron, or ion beams can be highly dependent on the local context in which the defect resides.
The performance requirements for defect detection on patterned wafers depend on the maturity of the semiconductor process. Figure 3 shows that the sensitivity requirement of patterned wafer inspection decreases when a process moves from R&D through the yield ramp to volume production. Some high-throughput tools that primarily monitor yield excursions in the volume production phase exhibit sufficient sensitivity to be useful in yield learning, which may continue even when product yields exceed 80%. Data from these yield-monitoring tools can be transferred to the more sensitive yield-learning tools that brought the process through the yield ramp. The yield-learning tools conduct further investigations of wafers exhibiting defects of specific interest. Thus, defect detection tools that dominate the yield ramp still serve a function during volume production. The throughput requirement for patterned wafer defect inspection rises dramatically when a semiconductor process matures. Defects abound at the beginning of the process R&D phase, and they can occur across vast regions of a wafer. A tool with a relatively low scan speed can find a defect in a very short time. However, defect detection becomes exceedingly difficult at the end of this phase, when it takes about an hour for a defect inspection tool to detect a statistically significant sample of fault-generating defects on 200-mm wafers, each containing about 500 SRAMs (see upper curve in Figure 2). Defects become exceedingly scarce as the process enters the yield ramp phase, precisely when the fab load increases, yet they can still generate enough electrical faults to prevent profitability. At the end of the yield ramp a defect inspection tool has to inspect 10 200-mm wafers per hour to enable yield learning. At that throughput, the tool takes about 6 minutes to detect a statistically significant sample of fault-generating defects on 200-mm wafers, each containing about 70 microprocessors (see lower curve in Figure 2). In volume production, such a tool must inspect 30 wafers/hr just to identify process excursions in a timely manner.11
As wafer size increases it will become exceedingly important to better understand wafer-to-wafer variability, since without an increase in scan speed, the equivalent scanned area will come from fewer wafers. Given no improvement in scan speed at these wafer size transitions, IC manufacturers will need to alter their sampling plans to balance the desires of total scanned area versus the number of wafers scanned. Figure 4 illustrates the throughput requirements of patterned wafer inspection in terms of scan speed, which is independent of wafer size.
Table I: Patterned wafer inspection tool technology requirements. Table I shows how the process life cycle influences other requirements of patterned wafer inspection tools, such as nuisance counts, sizing error, count repeatability, and tool-to-tool bias. Yield engineers need precise estimates of the number and size of defects during the early stages of process development, but they will accept an increased nuisance defect rate to help achieve higher sensitivity. During process R&D, defect reduction work is more engineering intensive, and more time can be allotted to distinguish between nuisance defects and killer defects. However, during high-volume production, detection tools and their associated recipes play a critical part in the control of process tools. They must detect killer defects with great confidence, which requires a clear distinction between a defect signal and noise induced by process variation. A volume production facility simply cannot afford to spend technician time to look at nonkiller defects. Similarly, control charts and reviewed defects cannot be confounded by nuisance counts and increased tool-to-tool bias. Manufacturing personnel need to identify the correct defects and rely on matched data, no matter which tool is used for defect inspection or review.
Figure 5: Defect detection data cycles of copper dual damascene based on Sematech process flow for the 180-nm technology node. Figure 5 compares the relative data cycles of key inspections of copper dual damascene, the likely choice for global interconnect for the 180-nm technology node. The horizontal axis lists the process steps of copper dual damascene, which may repeat between 5 to 10 times within a full VLSI process, making global interconnect the process module with the highest number of defects. However, similar patterned wafer inspections occur in other modules of a VLSI process. Beyond the 250-nm node, the vast majority are likely to fall into one of three categories: post-CMP inspection, high-aspect-ratio inspection (HARI), and afterdevelop inspection. The data cycles of different defect inspections vary greatly. For example, an inspection at the head of an arrow in Figure 5 evaluates all the process steps between the head and the tail of the arrow. Thus the post-CMP inspection covers all process steps of dual damascene. Many wafer fabs also intend to conduct a post-canal-etch inspection, an example of HARI that localizes the sources of defects to fewer process steps. In the absence of such short-cycle inspections, a via etch problem could go unnoticed for more than a day, which would put a large number of wafers at risk in a volume production facility. Afterdevelop inspection may even capture systematic lithography defects in time to perform rework, which can increase line yield significantly and prevent yield crashes through early defect detection. Post-CMP Inspection.The effects of buried patterning in CMP wafer inspection make the challenges of post-CMP inspection resemble those of patterned wafer inspection more closely than those of unpatterned wafer techniques. A detailed pictorial description of the nature of post-CMP inspections makes any further depiction of the related process cross sections superfluous, and those inspections described are likely to continue past the 250-nm node.6 However, deploying the copper dual-damascene solution for global interconnect will most likely increase the number of CMP-related defect classes, seriously challenging the technology. Copper dual damascene will also replace most intermetal dielectric polishes with copper polishes, which will generate some of the surface failure modes depicted in Figure 1.
High-Aspect-Ratio Inspection. These inspections present a special challenge because defects that reside below the wafer surface are harder to capture. HARI sensitivity requirements are thus tougher than other forms of patterned wafer inspection, as Figure 6 shows. The challenge occurs at many stages of the fabrication cycle, including shallow trench isolation and local interconnect. The first-level contacts exhibit the highest aspect ratios encountered during any inspection. They are likely to exceed 6 by 1999 and grow to 12 by 2012. Adjacent first-level contacts may also vary in depth, because they may contact both polysilicon and the active area, which are not coplanar. Dual-damascene structures, which are likely to prevail by the year 2000, consist of combinations of canals that contain interconnect lines and vias between interconnect layers. Their combined aspect ratios may exceed 5 by 2006.20 The difficulty of detecting defects in vias is exacerbated by the fact that there will be typically 1011 vias on a 300-mm product wafer per layer of vias. Defects in 10 to 20 of those 1011 vias would have a significant detrimental effect on yield. Adding to the challenge of detecting such via defects is the difficulty of directing interrogating agents (i.e., photons, electrons, ions) onto the bottom of the narrow vias, which is compounded by the difficulty of having the signal energy make its way back out of the via to a detection system. No feasible methods have been conclusively demonstrated at the process R&D phase and certainly not at the volume production phase. Afterdevelop Inspection. Historically, this type of inspection has consisted of two parts: a macroinspection, where an operator scans a wafer under bright light, and a microinspection, where an operator searches for defects under a microscope. The operator typically finds defects visible to the naked eye during the macroinspection, while smaller defects would have to be detected during the microinspection. Cost of ownership drives the automation of afterdevelop inspection, which can occur more than 25 times during wafer fabrication. These tools must thus be relatively inexpensive and scan at high speed. Automated macroinspection should function as a substitute for the operator's eyes and match or exceed the eyes in sensitivity, i.e., approximately 50 µm. The macroinspection occurs at wafer level, and throughput should exceed that of a wafer stepper. Just like an operator, macroinspection must provide an analysis of systematic defects that can be fed back to the production tool. The cost of ownership of a macroinspection tool must also be lower than that of an operator performing a bright light scan. Automated microinspection acts as a substitute for an operator running an optical review station. It occurs at the die level and must be sensitive to submicron defects. This requires ~500x magnification, conventional optics, and a wide field of view. Automated microinspection must also perform automatic defect classification, and low cost of ownership requires a throughput that matches that of a wafer stepper. Sematech conducted a tool definition workshop for afterdevelop inspection in Austin, TX, on January 29, 1997, at which 32 delegates from member firms and the supplier community set out to define the basic configuration and performance specifications of an automated tool. Workshop participants specified the requirements for macroinspection but were unable to achieve consensus on microinspection. They concluded that automated macroinspection was a real technology gap because no supplier offered a satisfactory solution. The participants determined that solutions for automated microinspection exist, but their cost of ownership was too high. Cost of ownership also drove the tool configuration discussion at the workshop. A stand-alone afterdevelop inspection tool that added less than $0.50 per inspection to the cost of a wafer would meet the requirements of the semiconductor industry. An on-track solution would require a cost of ownership of less than $0.25 per inspection. The tool configuration preferences vary from chipmaker to chipmaker. Some IC suppliers have demanded a combined, stand-alone macro/micro tool, whereas others prefer an on-track macroinspection. All chipmakers that participated in the workshop consider the pursuit of an automated macroinspection solution that meets the cost-of-ownership requirements a worthwhile endeavor. The majority of the participating IC manufacturers are willing to continue with existing solutions for microinspection. They intend to reduce the cost of ownership of microinspection through sampling plans that anticipate and identify systematic faults at the expense of capturing isolated random defects. Unpatterned Wafer Inspection Unpatterned wafer inspection tools that analyze bare silicon wafers and wafers with various blanket films have been commercially available since the 1970s, which has allowed yield enhancement teams to conduct particle-per-wafer-per-pass (PWP) experiments on many generations of process equipment. PWP experiments can be conducted to check the defect counts of starting material, photoresist spin tracks, dielectric deposition reactors, and CMP equipment. Only the graininess of metal films has interfered with unpatterned wafer inspection of metal deposition steps to date. Engineers and technicians simply count the number of defects on a test wafer using an unpatterned wafer inspection tool, run the test wafer through a piece of process equipment, and recount the number of defects. Corrective action hopefully results in a reduced defect count, which, given a positive correlation between PWP defect count and functional yield, increases the number of functioning product chips. A strong correlation between PWP data and functional test data also demonstrates the predictive qualities of unpatterned wafer inspection. PWP experiments run on such short cycles that they can be used to evaluate the defect generation rates of individual process tools, individual chambers within process tools, and cluster tools that perform multiple process steps. For example, the dielectric deposition of dual damascene consists of two interlayer dielectric depositions and two barrier-layer deposition steps. By using different recipes, a process engineer can count the number of defects generated by the complete dielectric deposition or examine the defectivity of its constituent steps. Because they consume many test wafers, PWP experiments cannot be conducted on a large scale. However, the inspection of unpatterned starting material to identify surface roughness, crystal-originated pits, and true particulates can be considered as an in-line experiment. The cost of such inspections is thus relatively low.
Table II: Unpatterned wafer inspection tool technology requirements. The requirements for bare wafer inspection include the needs for monitor wafer inspection as well. Again, because of the different expectations of the fab engineer for defect detection tools for the different product stages, the technology requirements are different for each application. The set of parameters common to all types of unpatterned wafer inspection applications are shown in Table II.
Figure 7 shows that the sensitivity requirements for defect detection on unpatterned wafers depend on the film and substrate. The most stringent requirements come in the earlier process stages. Note also that the wafer backside requirements are not scaled with the critical dimension, but rather are based on lithography depth-of-focus considerations. In Situ Sensors In situ sensors have the potential to generate defect and fault data in real time. Sensors can detect deviations from the normal process conditions in a chamber and either emit a fault signal or induce automatic corrective action. For example, the process steps identified in Figure 5 can, in principle, be monitored by in situ sensors. Thus, if the correlation from sensor data and functional yield were known, scrap decisions could occur automatically and in real time. Applications for in situ sensors exist in many process tools, because the scope of the sensors exceeds particulate detection. Sensors detect many potentially damaging chemicals, including metal ions that can alter the performance of MOS devices. However, suppliers of sensors, suppliers of process equipment, and chipmakers need to settle many issues before sensors can become a standard feature on process tools. These include sensor communication standards, which would provide compatibility between sensors, the data acquisition system, and, in the future, tool controllers. A data format standard would enable a merger of the real-time sensor database and the defect database. It would also allow users to select third-party software suppliers to analyze both in situ and defect databases once a standard interface to third-party software is available. Moving data between two tools requires a standard interface to the host computer. A standard interface to the process tools would enable decisions made by the data system to be communicated to individual tools. Many of these capabilities are being addressed by SEMI computer-integrated manufacturing and automated process control frameworks.21 Real-Time Defect Classification The final major challenge of shortening defect data cycles consists of providing real-time defect/fault classification capabilities for in situ monitors and defect inspection equipment. The classification of defects detected by optical means or scanning electron microscopy (SEM) is now relegated to defect review stations, which have to redetect the defect found by the inspection tool. Defect characterization becomes a two-step process consisting of detection and review. Optical defect review is also becoming increasingly difficult since many killer defects are no longer detectable by optical means. According to the NTRS, even the 250-nm technology requires SEM-based defect review and classification solutions.
Table III: Automatic defect classification technology requirements.
Table III outlines the technology requirements for automatic defect classification (ADC). For yield-monitoring applications such as back-end metal layers in high-volume manufacturing, optical-based redetection and ADC will be extendable into the 150- and 130-nm technology nodes. However, for yield ramp engineering applications (30—70% minimum feature size resolution) at these nodes and front-end-of-line applications at the 250- and 180-nm nodes, SEM-based solutions are necessary as optical redetection and ADC falls off dramatically at around 250 nm. In this regard, SEM-based review and ADC solutions will be necessary in many applications, at earlier technology nodes for front end of line and later for back end of line. Detection tools that provide in-line ADC capability based either on image or light scatter analysis will also be necessary to assist in accelerating cycles of learning, as well as optimized SEM-based tool utilization. A combination of optical and SEM-based solutions will be necessary to classify those defects not redetectable via SEM (e.g., previous layer defects) and those not redetectable via optics ( Defect Detection Solutions IC feature sizes, the maturity of a process, and the length of a learning cycle jointly define the requirements for defect detection solutions. Feature sizes push sensitivity requirements, the position in the process life cycle determines throughput requirements, and capital productivity drives the trend toward shorter learning cycles. Solution providers must therefore determine the scope of their solutions by designing for sensitivity and throughput ranges as well as learning rates.
Table IV: Potential technology solutions for patterned wafer inspection (includes date needed and sensitivity requirements). The defect reduction technology working group can assist defect detection solutions providers by identifying technology candidates that could effectively detect defects across different ranges of feature sizes, phases of the process life cycle, and varying learning cycles. For example, Table IV lists potential technology solutions for patterned wafer inspection as a function of technology node and phase of the process life cycle. It clearly indicates a gap between the process R&D phase and the more mature phases, which results from the stringent sensitivity requirements of the process R&D phase and the differential in scan speed requirements illustrated in Figure 5. Only tools based on SEM, extreme ultraviolet, and x-ray technology are expected to meet the sensitivity requirements of this phase, which consistently equals one-third of the minimum circuit feature size. None of these technologies will likely be able to scan at rates faster than 300 cm2/hr before 2005, at least in configurations that semiconductor manufacturers can afford. Chipmakers will probably want to exploit less exorbitantly expensive optical and UV solutions to their sensitivity limits. Optically based tools will therefore search for defects in mature processes for at least a decade, unless someone invents a completely novel approach.
Table V: Potential technology solutions for high-aspect-ratio inspection (including date needed). Table V shows a completely different picture for high-aspect-ratio inspection, where sensitivity requirements equal one-third of the minimum feature size throughout the process life cycle. The table assumes that UV-based tools cannot capture contaminants smaller than 40 nm with the desirable rate of 90%. Consequently, new inspection tool paradigms must be developed for the yield ramp and volume production phases of the 100-nm technology node. Unfortunately, the foreseeable solutions run into the aforementioned cost barriers, which makes HARI a fertile ground for the pursuit of novel approaches. The expected high price tag of defect inspection tools may cause many companies to reevaluate the cost/benefit relationships of defect detection. For instance, most current cost-of-ownership models do not include defect inspection. Consequently, semiconductor manufacturers are continuously tempted to underinvest in inspection tools. They argue that inspection adds no direct value to the wafers so they focus their resources elsewhere. However, a suboptimal number of inspection steps introduces substantial risk of yield loss, the cost of which has to be balanced against the cost of ownership of the inspection equipment.22 Inspection equipment, no matter how expensive, is therefore here to stay. The increasing diversity of process failure modes will force manufacturers to purchase a plethora of inspection tools, but an emphasis on in situ solutions may require them to buy fewer numbers of each tool. The cost of ownership of in situ sensors is orders of magnitude below that of defect inspection tools. In situ methods can detect both defects and process problems in real time, which enables process engineers to save large amounts of material by shutting down equipment or even the whole line. The high cost of ownership of defect inspection equipment may thus serve as an impetus to resolve the outstanding standardization and compatibility issues associated with in situ methods. Resolution of these issues will also enhance the effectiveness of ADC. The trend toward shorter learning cycles should continue. The great variation in the learning cycles of different defect detection methods may enable yield improvement teams to engage in innovative yield management methods. Given access to integrated data analysis tools, yield engineers may be able to establish correlations between data from in situ sensors, data from inspection tools, and functional test data. Strong correlation between in situ sensor data and functional test data would give in situ methods a direct predictive capability. Defect detection methods with intermediate learning cycles (patterned wafer inspection) would only be used on a troubleshooting basis. The development of predictive yield models during the early phases of the process life cycle would reduce the cost of defect detection during volume production by relegating patterned wafer defect inspection tools from in-line to at-line equipment. More types of increasingly expensive inspection tools will have to be purchased as IC processes become more complex. However, an emphasis on in situ methods and integrated solutions may substantially reduce the instances of each tool type a semiconductor manufacturer has to buy. Defect detection and yield management are thus, at least in theory, likely to remain affordable. Acknowledgments Portions of this article were adapted from The National Technology Roadmap for Semiconductors 1997 revision and used with permission. The authors wish to acknowledge the members of the defect reduction technology subgroup that worked on defect detection. They include Ram Akella, Bobby Bell, Brian Duffy, Terry Francis, Pat Gabella, Milt Godwin, Mike Grobelny, Matt Ivanis, Fred Lakhani, Pat Lamey, Tom Larson, Greg Starr, and Brian Trafas. The authors would also like to thank Vijay Sankaran and Brad Van Eck for reviewing this article. References 1.Jensen D, Gross C, and Mehta D, "New Industry Document Explores Defect Reduction Technology Challenges," MICRO, 16(1):35—44, 1998. 2.Stapper C, and Rosner R, "Integrated Circuit Yield Management and Yield Analysis: Development and Implementation," IEEE Transactions on Semiconductor Manufacturing, 8(2):95—101, May 1995. 3.Weber C, Moslehi B, and Dutta M, "An Integrated Framework for Yield Management and Defect/Fault Reduction,"IEEE Transactions on Semiconductor Manufacturing, 8(2):110—120, May 1995. 4.Moore G, "Progress in Digital Integrated Circuits," IEDM Technical Digest, p 11, 1975. 5.The National Technology Roadmap for Semiconductors, San Jose, SIA, pp 163—178, 1997. 6.Dennison C, "Developing Effective Inspection Systems and Strategies for Monitoring CMP Processes," MICRO, 16(2):31—41, 1998. 7.Shapiro A, James T, and Trafas B, "Advanced Inspection for 0.25-µm-Generation Semiconductor Manufacturing,"in Proceedings of SPIE 22nd Annual International Symposium on Microlithography, Bellingham, WA, SPIE, pp 445—451, 1997. 8.Seliger M, and Nasr MB, "Inspecting Wafers Using the Orbot-W720 at Metal ASI," presented at Applied Materials Process Diagnostic and Control User Group Meeting, Santa Clara, CA, February 1998. 9.Lukaszek W, Yarbrough W, Walker T, and Meindl J, "CMOS Test Chip Design for Process Problem Debugging and Yield Prediction Experiments," Solid State Technology, 29(3):87—93, 1986. 10.Weber C, "Generic Test Chip Formats for ASIC-oriented Semiconductor Process Development," in Proceedings of IEEE/ICMTS, New York, IEEE, pp 247—252, 1993. 11.Kaempf U, "Statistical Significance of Defect Density Estimates," in Proceedings of IEEE/ICMTS, New York, IEEE, pp 107—113, 1988. 12.Alcorn C, Dworak D, Haddad N, et al., "Kerf Test Structure Designs for Process and Device Characterization," Solid State Technology, 28(5):229—235, 1985. 13.Cunningham J, "The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing," IEEE Transactions on Semiconductor Manufacturing, 3(2):60—71, May 1990. 14.Silverman P, "Capital Productivity: Major Challenge for the Semiconductor Industry," Solid State Technology, 37(3):104, 1994. 15.Iansiti M, and West J, "Technology Integration," Harvard Business Review, May—June, pp 69—79, 1997. 16.Weber C, "Accelerating Three-Dimensional Experience Curves in Integrated Circuit Process Development," master's thesis in management of technology, Cambridge, MA, Massachusetts Institute of Technology, May 1996. 17.Weber C, Rosner J, and Chang P, "The Role of Self-Directed Work Teams in a Concurrent, Multigeneration Process Development Effort," in Proceedings of IEEE/SEMI/ASMC, Mountain View, CA, SEMI, pp 322—327, 1997. 18.Weber C, "Standard Defect Monitor," in Proceedings of IEEE/ICMTS, New York, IEEE, pp 114—119, 1988. 19.Weber C, "A Standardized Method for CMOS Unit Process Development," IEEE Transactions on Semiconductor Manufacturing, 5(2):94—100, May 1992. 20.The National Technology Roadmap for Semiconductors, San Jose, SIA, pp 99—113, 1997. 21.Butler S, Hosch J, Diebold A, and Van Eck B, "Sensor-based Process and Tool Control," Future Fab International, 1(2):315—321, 1997. 22.Wang E, Holtan M, Akella R, et al., "Valuation of Yield Management Investments," in Proceedings of IEEE/SEMI/ASMC, Mountain View, CA, SEMI, pp 1—7, 1997. Charles Weber is a Hewlett-Packard assignee at Sematech (Austin, TX), where he manages the defect detection project. He has been with HP for 16 years, starting as a process engineer in an IC manufacturing facility. He subsequently moved to the company's IC Process R&D Center in Palo Alto, CA, where he worked primarily on microelectronic test structures and yield management. Weber has a BS in engineering physics from the University of Colorado (Boulder); an MS in electrical engineering from the University of California, Davis; and an MS in management of technology from the Sloan School of Management at the Massachusetts Institute of Technology. (Weber can be reached at charles.weber@ibm.net.) David Jensen is program manager for defect reduction technology at Sematech, Austin, TX. He is an Advanced Micro Devices assignee and while there, as a member of the technical staff, his primary responsibilities were development and deployment of contamination-free manufacturing strategies. Before joining AMD, Jensen was at Digital Semiconductor for five years, where he was engineering supervisor of the Fab 6 CFM group. He served as cochair of the DR CCTWG for the 1997 revision of the SIA NTRS. He has also worked extensively in the semiconductor process equipment industry for ASM America and Spectrum CVD, holding numerous positions in design and engineering with emphasis on contamination control in process equipment. He has written numerous papers and has presented widely on contamination control and defect reduction technology. Jensen holds a BS in mechanical engineering from Arizona State University (Tempe). (Jensen can be reached at 512/356-3756, or via E-mail, david.jensen@sematech.org.) E. Dan Hirleman, Jr., PhD, is a professor of mechanical and aerospace engineering and affiliated with electrical engineering at Arizona State University (Tempe). He also serves as assoicate dean for research in ASU's College of Engineering. His research focuses on optical measurement techniques, including surface characterization and sensors for semiconductor manufacturing, particle and flow diagnostics, and design for inspectability. Hirleman is director of the ASU Consortium for Metrology of Semiconductor Nanodefects, whose members include 10 companies interested in industry-university research collaboration on wafer inspection. He received his BS, MS, and PhD in mechanical engineering from Purdue University. Hirleman has published more than 100 papers, holds four patents, and has presented more than 60 invited lectures in 10 countries. (Hirleman can be reached at 602/965-3895 or hirleman@asu.edu.)
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Figure 3: Sensitivity requirements for patterned wafer inspection from NTRS.
Figure 4: Patterned wafer defect inspection scan speed requirements from NTRS.
Figure 6: Sensitivity requirements for high-aspect-ratio inspection from NTRS.
Figure 7: Sensitivity requirements for unpatterned wafer inspection.
250-nm surface/pattern defects).
