Developing yield modeling and defect budgeting for 0.25 µm and beyond

Daren L. Dance, Wright Williams & Kelly; David Jensen, Sematech/AMD; and Randall Collica, Digital Semiconductor

(Second in a series)

the 1997 revision of The National Technical Roadmap for Semiconductors (NTRS) addresses the entire yield learning process, including the impacts on device performance and reliability.¹ The four focus topics—yield modeling and defect budgeting, defect detection, defect sources and mechanisms, and defect prevention and elimination—correspond with the learning cycle typical of yield engineering and defect reduction. The goal of the yield model and defect budget (YMDB) team is to understand how defect sources in production equipment and environments relate to electrical faults in semiconductor devices. This team has established equipment, electrical, and process defect budgets to guide future defect reduction requirements.²

The first roadmap was published in 1992 under the sponsorship of the Semiconductor Industry Association (SIA) to provide a common vision and to increase cooperation in precompetitive semiconductor research and development.³ The work behind NTRS  was motivated by the rapidly increasing complexity in semiconductor technology. The roadmap was revised in 1994 and 1997.^1,4 Each revision takes a 15-year view of semiconductor technology requirements for R&D and manufacturing; each includes an updated roadmap of targets for equipment defect contribution limitations. These targets, produced by the YMDB team, are meant for semiconductor equipment developers and suppliers. The team also looked at the state of yield modeling and yield management strategies to identify technology needs, challenges, and potential solutions.

YMDB Challenges

Several difficult challenges were identified by the YMDB team. Defect budgets require frequent revalidation and updates as information about future processing technologies becomes available. Yield models need to better consider complex integration issues and parametric yield losses for future technology nodes. Future defect models must consider electrical characterization information, with reduced emphasis on visual inspections and analyses. Defect modeling of emerging technologies with high-aspect-ratio contacts, new materials, and combinations of channels and vias in dual-Damascene structures will continue to be a difficult challenge. The development of a statistical means of accurately dealing with near-zero-defect-adding data with high variation coefficients is a formidable data reduction and yield modeling task. Through the use of advanced test structures and modeling techniques, the fundamental challenge in the area of process-critical materials is to understand the correlation between impurity concentration and device yield, reliability, and performance. Real-time yield models are necessary that will allow tools to automatically self-monitor their processing status in order to predict yield excursions, failures, and faults, and to initiate corrective actions.

Defect Budgeting Method

The electrical D^₀ (defect density) targets are the basis of all yield learning and defect reduction. These targets are listed in Table I for each technology node as noted in the overall technology characteristics chapter of the latest NTRS. ⁵ The defect budget technology requirements are based on the negative binomial yield model, where Y is the defect-limited yield, A is the critical area of a device, D^₀ is the defect density, and is the cluster factor:⁶

Year of First Product Shipment (Technology Generation)	1997 (250 nm)	1999 (180 nm)	2001 (150 nm)	2003 (130 nm)	2006 (100 nm)	2009 (70 nm)	2012 (50 nm)
Critical defect size (nm)	125	90	75	65	50	35	25
Electrical D0/m2, 60% yield	1940	1712	1512	1353	1119	939	776
Microprocessor area (mm2 )	300	340	385	430	520	620	750
Mask levels	22	23	23	24	25	27	28
Faults per mask level	88	74	66	56	45	35	28

Table I: Electrical defect density targets. (Source: 1997 NTRS)

For this revision, = 2 and Y = 60%, or the yield expected in the first year of manufacturing production. Other yield modeling methods could have been used, but the flexibility of the negative binomial and the availability of Sematech validation using this model were major factors in selecting this model. By selecting the appropriate cluster factor, the negative binomial model can approximate other common yield models (see Table II).^7,8

Model	Formula	Binomial Cluster Factor
Seeds		= 1
Murphy		~ 4.5
Poisson		>7

Table II: Common yield models.

The 1994 revision based the defect budget on a 90% overall sort yield in the first year of production and was calculated according to the predicted maximum ASIC die area at each technology node. For the 1997 document, overall electrical defect densities for both 60 and 80% sort yields were calculated using the first- and third-year die areas for microprocessors and DRAMs, and for 60% sort yield in first-year ASIC production. A first-year yield of 60% was regarded as more realistic than 90% (from the 1994 NTRS ), given the large chip areas represented by both the microprocessor and ASIC trends.⁹ The defect budgets in Table III show the 60% first-year requirements.

	Year of First Product Shipment (Technology Generation)
Process Tool	1997 (250nm)	1999 (180nm)	2001 (150nm)	2003 (130nm)	2006 (100nm)	2009 (70nm)	2012 (50nm)
Front end of line (FEOL):
Doping	860	376	231	149	70	27	11
Interconnect	1076	471	289	186	87	33	14
Surface preparation	1642	718	441	284	133	51	21
Thermal/thin film	850	372	228	147	69	26	11
Back end of line (BEOL):
Interconnect	605	265	162	105	49	19	8
Planarization	1418	620	380	245	115	44	18
Surface preparation	1718	751	461	297	140	53	22
FEOL/BEOL:
Lithography	648	284	174	112	53	20	8
Metrology/inspection	1195	523	321	207	97	37	15
Wafer handling	30	13	8	5	2	1	0.4

Table III: Defect budgets at 60% yield during the first year of production. (Source: 1997 NTRS)

The requirements for the 1997 250-nm technology node use the results of a 1996 study of current defect levels at Sematech member companies.¹⁰ The defect budget technology requirements were extrapolated from the median process-induced defect (PID) value for each process module by considering increases in area and complexity, and shrinking feature size. The inclusion of the complexity increase appears for the first time in the 1997 NTRS revision:

The extrapolation uses the above equation, where PID is in defects per square meter, F is the average faults per mask level, and S is the minimum defect size. N refers to the technology node (see Table I). Each entry in Table III refers to a typical tool within the process zone. Since future tools and processes are not known, this roadmap assumes that no new process, material, or tool will be accepted with a greater PID budget than those used for current processing methods.

This defect budgeting method is a worst-case model since all process steps are assumed to be at minimum device geometry despite the fact that most processes have layers with more relaxed geometries. Since manufacturing uses the same tools at both minimum and relaxed geometries, the use of a worst-case defect budgeting model may be prudent. Some suppliers may provide tools for manufacturing the relaxed geometries that do not meet NTRS defect budget requirements.

Yield Model Validation Methods

The defect budget requirements for the 250-nm technology node use the results of a 1996 study of current PIDs conducted by Wright Williams & Kelly for Sematech. The validated targets were derived from particle per wafer pass (PWP), PID, and electrical test measurements collected from participating Sematech member companies and from the consortium's project information. To address confidentiality concerns and other manufacturing differences, all inputs were normalized to a 90% yield basis at a minimum defect size sensitivity of 0.08µm. These normalized data sets were then mapped to the consortium's 0.25-µm process and tool set prior to analysis. The data collection and validation steps are summarized as follows:

• Collect member company data.

• Map to Sematech tool list.

• Model member company yield estimate.

• Map to Sematech 250-nm process.

• Scale to 90% yield.

• Compare all scaled member company estimates.

• Eliminate outliers and check data sufficiency.

• Determine 50th percentile of validated tool estimates.

• Renormalize to 90% yield.

The Sematech defect targets were then scaled to 60% yield using the first equation cited above. The 1997 NTRS defect budgets were based on the scaled targets from the consortium, which were extrapolated to future technology nodes using the second equation detailed above.

Each validation source provided one or more estimates. Tool-by-tool PWP measurements resulted in validated tool-by-tool PWP defect targets. Estimating tool-by-tool PID targets was more complex. The PID measurements focus on a process zone, not a specific tool. The yield model converts zone PID measurements to tool measurements by identifying the tools used in a process zone and allocating the PID estimates of fault density to each tool used. This allocation method builds on the reentrant nature of semiconductor processing. Since process zones are not identical, the differences between the process zone tool sets help to identify relative contributions by tool. This effect is illustrated in a simple example in Table IV, in which tool B clearly has a greater contribution to PIDs than tool C.⁷

Zone	Zone PID	Tool A	Tool B	Tool C	Tool D
1	180	60	Not used	60	60
2	360	120	120	Not used	120
3	210	Not used	70	70	70
Total PIDs	­	180	190	130	250
Steps	­	2	2	2	3
Avg. PIDs	­	90	95	65	83.3

Table IV: Estimating particles per wafer pass from process-induced defects.

Impacts of Defect Budgets

The continuation of Moore's Law is the primary planning assumption for NTRS. To continue this trend requires scaling the cost per bit or cost per transistor by about 25—30% from one technology generation to another, as shown in Figure 1.^11,12 Moore's Law is based on mature process yields, which have ranged from 30—40% in the 1970s to 80—90% today. To maintain this unprecedented level of productivity improvement, the continued reduction of defects in process equipment remains paramount.

Figure 1: Microprocessor cost per transistor.

While NTRS defect budgets appear to be very aggressive, cost of ownership (COO) analysis suggests that they could be even more so. In Figure 2, COO estimates for a 300-mm lithography cell were compared using the lithography defect budget from Table II.¹³ The initial cost of the lithography cell was assumed to be $9.1 million in 1997. This analysis assumes that the equipment will meet the defect budget and that all other costs not for equipment purchase and installation will remain constant. The COO was simulated for equipment purchase and installation cost by increasing 2, 4, and 6% between each technology node.¹⁴ The figure shows a reduced cost per wafer caused by a reduced amount of defects per node. The historical trend indicated by Moore's Law has been maintained in spite of inflation, which in the 1970s ranged from 10—15%. Inflation must continue to be offset with defect reduction and other productivity gains. Thus, to continue to follow Moore's Law of historical cost reduction, the 1997 NTRS defect budgets need additional downward revision for post-2003 technology nodes.

Figure 2: Cost of ownership (COO) trends.Table V: Estimated mean wafers between handling defects. (Source: 1997 NTRS)

Yield improvement has never been the sole impetus for keeping Moore's axiom in motion. Productivity improvement through device-size reduction, design efficiency, and increases in manufacturing productivity are other drivers. Furthermore, the law is based on mature production, not on a product's first year of introduction. While the defect budgets are based on 60% yields, COO analysis indicates that there is still more productivity to be gained by moving from 80—90% to 85—95% yields.

The bottom line is, yield improvement was necessary to maintain the historical trend indicated by Moore's Law. It is naive to assume that we can continue this trend without continuing to improve the yield driver. This contradicts some conventional thinking that posits that there is very little to be gained from increasing yields beyond the 80—90% level for mature products. Figure 2 raises an early warning that if the semiconductor industry only follows the NTRS defect budget, defect reduction will be a net contributor to Moore's Law from 1997 to 2003, but the industry will require either more aggressive defect reduction or other productivity gains to maintain this principle from 2003 to 2012.

Yield Modeling Issues and Challenges

Key business metrics rely on the success of rapid yield improvement and the associated disciplines of defect allocation, formation, transport, deposition, detection, characterization, reduction, and elimination. The validation information provided by Sematech has significantly improved the quality of the defect budgets. This validation effort must continue with each new revision of the roadmap. In order to address future modeling challenges, there must be continued research to improve yield modeling techniques. The increasing dominance of nonvisual defects will further complicate yield modeling and defect budgeting. Thus, defect models have to better consider electrical characterization information and reduce emphasis on visual analysis. This will require research into new characterization devices and methods as well as an improved understanding of systematic and parametric impacts on device yield.

Interconnect process layers pose a particularly formidable challenge and have been identified as doing so in the technology requirements.¹⁵ The issues include the modeling of the yield impacts of ultrathin-film integrity, increased process complexity, and interconnect speed and transmission characteristics. Defect-to-fault transformations, kill ratios, and isolation techniques are also believed to be critical challenges as physical device dimensions and corresponding defect dimensions continue to shrink. One hindrance to yield modeling research is the current lack of state-of-the-art semiconductor processing capabilities in universities and other research centers.

As the number of defects per square meter shrink with technology improvements, the existing metric—defects per square meter—becomes less meaningful. Therefore the YMDB team proposed a new defect metric—mean wafers between defects (MWBD). This improved metric recognizes that defectivity is moving away from the random defect statistics and toward reliability statistics. Table V shows MWBD for handling defects.

Areas for YMDB Improvements

As the industry moves forward into succeeding technology generations, the following yield modeling and validation enhancements should be considered to improve the defect budget:

• Use of electrical data in yield models for mapping to process data, resulting in defect kill ratios.

• Increased use of parametric models, particularly for interconnect issues.

• Use of critical area extraction software at each process level during validation instead of assuming minimum geometries across the entire chip area.

• Acquisition of data at several points along the yield learning curve to understand the effect of clustering as yields improve.

• Verification of defect size (and type; e.g., scratches) distributions at various yield levels.

Continuous and ongoing validation and optimization of the defect budget with available benchmark data will ensure the budget's long-term usefulness.

Acknowledgments

Portions of this article were adapted from The National Technology Roadmap for Semiconductors 1997 revision. Used with permission. The authors want to acknowledge significant contributions by the following members of the NTRS YMDB team: Ram Akella, Robert Anderson, Ron Braken, Terry Francis, Ron Harris, Wojciech Maly, Venu Menon, Sanjiv Mittal, Paul Proctor, Ken Tobin, and Hank Walker. We further wish to thank Sematech's yield model development and validation team, led by Susan Cohen, Randy Williams, and Fred Lakhani. Significant validation support was also provided by Rick Jarvis, Tom Winter, and David Chamness.

References

1. The National Technology Roadmap for Semiconductors, San Jose, SIA, 1997.

2. "SIA Roadmap Update: New Definition, Advanced Defect Detection Tools Are Keys to Highway," MICRO, 15(2):14—21, 1997.

3. The National Technology Roadmap for Semiconductors, San Jose, SIA, 1992.

4. The National Technology Roadmap for Semiconductors, San Jose, SIA, 1994.

5. The National Technology Roadmap for Semiconductors, San Jose, SIA, p 165, 1997.

6. Stapper CH, "Modeling of Integrated Circuit Defect Sensitivities," IBM Journal of Research and Development, 27(6):549—557, 1983.

7. Lakhani F, Dance D, and Williams R, "0.25 Micron Integrated Circuit Yield Model Design and Validation," presented to the International IEEE Symposium on Semiconductor Manufacturing, San Francisco, October 1997. 8. Stapper CH, "Fact and Fiction in Yield Modeling," Microelectronics Journal, 20(1—2):129—133, 1989.

9. Jensen D, Gross C, and Mehta D, "Mapping the Roadmap: New Industry Document Explores Defect Reduction Technology Challenges," MICRO, 16(1):35—44, 1998.

10. Lakhani F, private communication, 1996.

11. The National Technology Roadmap for Semiconductors, San Jose, SIA, p 10, 1994.

12. The National Technology Roadmap for Semiconductors, San Jose, SIA, appendix B-1, 1997.

13. I300I Equipment Performance Metrics, Austin, TX, 1996.

14. Two COOL Cost of Ownership Luminator User's Guide and Reference: Version 2.2.2, Dublin, CA, Wright Williams & Kelly, 1997.

15. The National Technology Roadmap for Semiconductors, San Jose, SIA, pp 10—11, 1997.

Daren L. Dance is manager of applications R&D for Wright Williams & Kelly, Austin, TX. He is also a coinvestigator in a joint cost-modeling research project for environmental, safety, and health with Oregon State University. Before joining WWK, he was a senior member of the technical staff in operational modeling at Sematech, where he developed the consortium's initial yield models and managed cost of ownership projects. He was recently retained by Sematech to update and validate those yield models for 0.25-µm processes. Dance is cochair of SEMI's metrics cost of ownership subcommittee and is the YMDB team leader for the SIA's NTRS. He has a BS in engineering from Idaho State University (Pocatello) and was a staff engineer with American Microsystems in Pocatello. He is a member of IEEE and has published many technical papers on COO and yield modeling. (Dance can be reached at 512/349-4950.)

David Jensen is program manager for defect reduction technology at Sematech, Austin, TX. He is an Advanced Micro Devices assignee and while there, as a member of the technical staff, his primary responsibilities were development and deployment of contamination-free manufacturing strategies. Before joining AMD, Jensen was at Digital Semiconductor for five years, where he was engineering supervisor of the Fab 6 CFM group. He served as cochair of the DR CCTWG for the 1997 revision of the SIA NTRS. He has also worked extensively in the semiconductor process equipment industry for ASM America and Spectrum CVD, holding numerous positions in design and engineering with emphasis on contamination control in process equipment. He has written numerous papers and has presented widely on contamination control and defect reduction technology. Jensen holds a BS in mechanical engineering from Arizona State University (Tempe). (Jensen can be reached at 512/356-3756, or via E-mail, david.jensen@sematech.org.)

Randall Collica is a principal yield engineer for Digital Semiconductor, Hudson, MA. His primary interests are in information delivery, data analysis, SRAM fault analysis, yield modeling, fault tolerance, and experimental design and analysis. He has established the use of yield models for redundancy on advanced microprocessors containing onboard cache SRAMs. These models were used for line control and productivity optimization for VLSI products. He has a BS in electronic engineering from Northern Arizona University (Flagstaff). He worked for the Micro-Rel division of Medtronics and Analog Devices before joining Digital in 1987. He is a member of the IEEE.

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