MAPPING THE ROADMAP

New industry document explores defect reduction technology challenges

(First in a series)

David Jensen, AMD/Sematech; Charles Gross, Digital Semiconductor; and Dinesh Mehta, Semiconductor Research Corp.

The most critical factors affecting profitability in leading-edge, high-volume IC manufacturing are customer satisfaction or, generally speaking, products which meet performance, functionality, price, quality, and reliability requirements; cost control and reduction; and time to market. In today’s marketplace, moderately higher average selling prices, which are necessary to cover higher manufacturing costs associated with low-yielding processes, coupled with market entry just months late, can have a dramatic impact on revenues and become the difference between profit and loss. Significant factors affecting both time to market and cost are the level of defects generated by the manufacturing process and the rate at which those defects are reduced.

Defects can be defined in the broadest sense as any actual outcome which deviates from the expected outcome. Possible defects include particles, contamination, ineffective control of physical and electrical parameters, device structure— related issues, process-to-process interactions including geometric effects, and design-process interactions. When yields are low—that is, when defect levels are high—the likelihood of adverse impacts on device quality and reliability increases.¹ Therefore, to achieve effective manufacturing, all defect types must be minimized.

Profitable IC manufacturers understand that yield is a major factor in maintaining profitability. These companies have comprehensive programs in defect reduction or yield engineering coupled with a general philosophy that all operators, technicians, and engineers must continually strive to reduce defect levels. Some fabs even operate under the premise that, in part, chipmaking is the business of defect control and reduction. This approach simply suggests that given robust designs and processes, meeting time-to-market goals and making the lowest-cost shipments can only be achieved with a strong focus on defect reduction.

Defects have many sources, including unit processes, integration of those processes, designs, process materials, material handling, inadequately trained people, and faulty or improperly operated manufacturing equipment. Based on the critical nature of defect reduction activities within all aspects of IC design and manufacturing, SIA’s Roadmap Coordinating Group (RCG) elevated the status of defect reduction (DR) technology, creating a DR subgroup of the Crosscut Technology Working Group (CCTWG) for the 1997 revision of The National Technology Roadmap for Semiconductors (NTRS).

Several factors prompted the elevated status of DR technology in the new roadmap. After analyzing fab yields over the last 25 years, VLSI Research reported in 1996 that mature fab yields had peaked at ~85% (without repair) in 1991 at a fab cost of $600 million to $700 million.² As fab costs continued to rise in the following years, mature fab yields actually dipped to ~80%, as shown in Figure 1. Continued increases in fab investment are not likely to boost yields incrementally in the years ahead. Yield advances will have to come through accelerated learning rates and reductions in the time it takes to achieve mature yields. Likewise, yield excursions and the overall ability to maintain high yields will become key metrics.

Figure 1: Mature fab yield and cost correlation.

After analyzing process diagnostics, VLSI also reported an acceleration in yield learning rates, which is underscored by the decreasing time span that the industry has experienced in achieving ~98% DRAM yields (see Figure 2).³ For these accelerated learning rates to continue, products in research and pilot production must reach significantly improved yield levels. For example, in order to achieve near-100% yield on 1-Gb DRAMs in their first year of production, it may be necessary to secure yield levels as high as 90% when the product and associated processes are transferred from development into manufacturing.³ Clearly, this far-reaching goal will not be achieved without significant improvements in yield modeling and defect budgeting, defect detection, identification of defect sources and mechanisms, and defect prevention and elimination. These are the main topics addressed by the DR technology section of the new NTRS as well as the “Mapping the Roadmap” series introduced here.

Figure 2: Time to achieve 98% yield.

Defect Reduction Cycle

The structure of the DR CCTWG roadmap aligns with typical yield learning and defect reduction methodology. The document focuses on the four key topics mentioned above: yield modeling and defect budgeting, defect detection, identification of defect sources and mechanisms, and defect prevention and elimination. Figure 3 illustrates the DR cycle of yield learning and improvement.

Figure 3: Defect reduction cycle.

When a new fab starts up or a new process or product is introduced, yield targets typically account for time to market, profitability, and other business factors. From these targets, defect budgets are calculated through the use of a yield model algorithm. Ultimately, defect budgets help determine control limits for in-line defectivity at each critical process step.

Next, the yield program focuses on detecting defects, or events which lead to defects, through the use of in-line and in situ monitoring equipment. In-line tools are limited for detection use since they rely on a physically detectable anomaly in the circuit and thus cannot characterize all defects; that is, failed chips or bits where no physical remnant is found—either in-line or on further diagnosis during failure analysis.

Before defects can be eliminated they must be traced to their source and their creation mechanisms fully understood. In this phase, the yield program uses a great deal of modeling and data reduction technologies in conjunction with in-line data, not only to characterize the defect mechanism but also to attempt to correlate the defect to some typically measured in-line parameter.

Finally, once a defect source is identified, measures can be taken to prevent or eliminate it. The topic of defect prevention and elimination deals with the determination of allowable levels of microimpurities in the manufacturing materials or the wafer environment. These yield detractors—and methods of overcoming them—can take many forms, from lower levels of contaminants in process materials and equipment to chip design changes that factor in certain critical process windows. The yield learning cycle is repeated after yield models are adjusted to account for what was ascertained during the process.

Key Messages

Defect reduction has been greatly expanded to address the entire yield learning process, including impact on device performance and reliability. As noted above, key business metrics rely on the success of rapid yield improvement as well as on defect allocation, formation, transport, deposition, detection, characterization, reduction, and elimination. These competencies crosscut both packaging and process technologies in addition to the facility infrastructure, device design, and process integration. The DR section of the 1997 NTRS includes the following key messages:

• Defect detection, inspection, and review technologies continue to be the foremost priority among DR engineers and scientists. The analytical tool sets must have much greater sensitivity at increased throughput with a much higher level of automated defect classification, defect data management, overall data analysis capability, factory-integrated data management, and other artificial intelligence capabilities. All of these factors must be developed further so a total system solution can be achieved to promote continued defect learning capabilities.

• To achieve tool defect density targets of 60% first-year yield and 85—95% yield in mature products, better contamination control within the equipment itself is mandatory. The ability to detect particulate and nonparticulate contaminants within the processing environments will be enabled by improved in situ monitoring during process and process tool development, in situ chamber cleaning, and defect-transparent materials. The role of modeling associated with contamination formation, transport, and deposition must be emphasized to help focus tool DR learning.

• Order-of-magnitude improvements in the purities of critical process fluids (gases, liquid chemicals, and UHP water) should not be necessary over the next two or three technology generations. A fundamental understanding of the impacts of individual contaminants on product yield and device performance is certainly prudent. The accompanying improvements need to be justified in chemical/gas manufacturing, distribution, and control technologies, which support chemical and gas purity levels two to three orders of magnitude greater than those measured within today’s processing environments.

• Defect-to-fault transformations, kill ratios, and isolation techniques are also critical challenges as physical device dimensions and corresponding defect dimensions continue to shrink.

Overall Roadmap Technology Characteristics

The basis for all yield learning and defect reduction are the electrical D_o (defect density) targets, shown in Table I, for each technology node in the overall technology characteristics chapter of the revised NTRS.⁴ The 1994 edition of the NTRS set such targets based on an overall sort yield of 90% in the first year of production.⁵ The targets were calculated based on the predicted maximum ASIC die area at each technology node.

Node (nm)	250	180	150	130	100	70	50
1st-yr. production	1997	1999	2001	2003	2006	2009	2012
1st-yr. DRAM size (mm2)	280	400	445	560	790	1120	1580
1st-yr. microprocessor size (mm2)	300	340	385	430	520	620	750
1st-yr. ASIC size (mm2)	480	800	850	900	1000	1100	1300
3rd-yr. DRAM size (mm2)	170	240	270	340	480	670	950
3rd-yr. microprocessor size (mm2)	180	205	230	260	310	370	450
1st-yr. DRAM Do @ 60% yield (per m2)	2079	1455	1308	1039	737	520	368
1st-yr. microprocessor Do @ 60% yield (per m2)	1940	1712	1512	1353	1119	939	776
1st-yr. ASIC Do @ 60% yield (per m2)	1212	727	685	647	582	529	448
3rd-yr. DRAM Do @ 80% yield (per m2)	1389	984	874	694	492	352	248
3rd-yr. microprocessor Do @ 80% yield (per m2)	1311	1152	1026	908	762	638	525

Figure 4: First-year chip sizes by technology node.

Figure 5: First-year electrical defect densities for 60% sort yield by technology node.

For the 1997 edition, overall electrical defect densities were calculated for both 60 and 80% sort yields using the first- and third-year die areas for microprocessors and DRAMs, and for 60% sort yield in the first year of ASIC production.⁴ Figures 4 and 5 compare first-year chip sizes and electrical defect densities, respectively. Particularly noteworthy are the aggressive defect densities for ASICs driven by chip sizes equal to the maximum field area of the steppers in use at that technology node. First-year yield of 60% is seen as more realistic than 90% in the first year (from 1994 NTRS), given the large chip areas represented by both the microprocessor trends and the largest lithography field used for ASIC chip areas. Likewise, third-year yields of 80% for leading-edge microprocessors are regarded as reasonable, considering the complexities of ¾250-nm design geometries and the astronomical numbers of transistors predicted by the roadmap.

Figure 6: First- and third-year chip sizes by technology node.

Figure 7: First- and third-year electrical defect densities for 60% and 80% sort yields, respectively.

Figures 6 and 7 compare first- and third-year chip sizes and electrical defect densities, respectively, for DRAMs and microprocessors. For DRAMs, these first- and third-year targets are low (especially if repair is also considered), but given the negative binomial formula used to calculate D_o:

where A is chip area and (set equal to 2.0) is the clustering factor, roadmap users can calculate overall electrical D_o and targeted yields for their own areas.

Difficult Challenges

Table II lists difficult challenges for technology before and after the 100-nm technology node. Defect budgets will have to be frequently revalidated and updated when information about future processing technologies becomes available. Yield models must better factor in complex integration issues and parametric yield losses for future nodes. Defect models will have to consider electrical characterization information, with reduced emphasis on visual inspection and analysis. Detecting defects associated with high-aspect-ratio contacts and combinations of canals and vias in dual damascene structures will continue to be among the most difficult challenges. Exacerbating this challenge is the need to couple high sensitivity with high throughput in detection tools—a trade-off typically accepted for optimization of tool performance for either baseline yield learning or production-line monitoring. Fault isolation complexity should grow exponentially and will represent an extremely difficult task of defining both horizontal-plane and vertical-layer fault location dimensions. Determining the underlying root causes of circuit failures that leave no detectable physical remnant is an extremely difficult task. A fundamental data reduction challenge is finding statistical means of accurately dealing with near-zero defect adder data that frequently exhibit high coefficients of variation.

Five Difficult Challenges 100 nm —Before 2006	Summary of Issues
Development, validation, and use of accurate defect budget models	Development of test structures for new nodes; correlated PID, PWP, product nspections, and in situ measurements; sampling and statistical issues with ultrasmall populations; impact of within-wafer variations on yield predictions.
Inspection of high-aspect-ratio contacts/vias/trenches	Poor transmission of energy into bottom of via and back out to detection system; large number of contacts and vias per wafer.
Correlation/validation of trace impurity specifications within process critical materials	Test structures and advanced modeling needed to determine impact of trace metallics, ions, and organics on device performance, reliability, and yield.
Fault isolation	Circuit complexity grows exponentially and ability to rapidly isolate failures on nonarrayed chips is needed.
Defect-free, intelligent equipment	Advanced modeling (chemistry/contamination), materials technology, s/w, and sensors are required in order to provide robust, defect-free process tools that predict failures/faults and automatically initiate PMs prior to defect formation.
Five Difficult Challenges <100 nm Beyond 2006—	Summary of Issues
Budgeting defect targets to new tools to new tools and processes	Requirements include parametric yield loss models; modeling complex integration issues; ultrathin film integrity modeling; better methods of scaling front-end process complexity that considers increased transistor packaging density.
Ability to rapidly detect defects, residues, and particles at critical size	Existing techniques trade off throughput for sensitivity, but at predicted defect levels, both throughput and sensitivity are necessary for statistical validity.
Minimize inspection costs in high-volume production environments	Equipment must effectively use real-time process and contamination control through n situ sensors. Inspection must occur during yield ramp and by exception only in a production environment.
Ability to accurately characterize defects	In addition to traditional defect density data, defect characteristic data will be necessary to enable continued yield learning. In-line defect detection data must include size, shape, composition, and the like, all independent of location and topology.
Failure analysis of nonvisual defects	Techniques are needed to enable sourcing of defects where no physical remnant is detected.

Table II: Difficult challenges in defect reduction technology before and after 2006. (Source: 1997 NTRS)

The fundamental challenge in process-critical materials is to understand the correlation between impurity concentration and device yield, reliability, and performance through the use of advanced test structures and modeling techniques. This must be done to find out if increasingly stringent contamination specifications are truly required and to provide early warning for tighter specs in those cases where they are warranted. Process tools must have the capability to automatically self-monitor, so that failures and faults can be predicted and preventive maintenance initiated.

Crosscut Requirements

As a CCTWG, the DR subgroup is responsible for interacting with every working group in order to help define the defect issues and challenges specific to each group. For the 1997 revision of the NTRS, the DR group contributed sections to process integration, devices, and structures; front-end processes; lithography; interconnect; and factory integration.⁴ Here are some highlights from each of these sections.

Process Integration, Devices, and Structures. In order to accelerate cycles of yield learning as cost pressures mount, DR efforts must rely more on predictive and diagnostic test structures that can be used in conjunction with more conventional in-line techniques. The process integration, devices, and structures roadmap classifies test structure into four areas—input materials, transistor structure, interconnect, and yield enhancement—for the purpose of gaining understanding in the following areas:

• The impact of trace-impurity levels (metallics, ionics) within input materials (water, chemicals, photoresists, gases, wafers).

• The in-line detection of very small levels of contaminants.

• The diagnosis/sourcing of invisible defects (that is, defects with no visible physical remnant or those created in sublevels that become increasingly inaccessible by more conventional means).

• Electrical detection and screens for special failure modes (both yield and reliability) associated with new processes and materials.

• Predictive wafer-level reliability test structures for portions of the architectures of the IC technologies and associated modeling.

Front-End Processes. Device performance depends on the levels of contamination (metals, particles) and defects (silicon structural, crystal originated particles, stacking faults) in front-end processes. The roadmap’s starting materials and surface preparation commentaries, technology requirements, and potential solutions address many of these DR challenges. Some of the critical thinking within front-end processes includes the following:

• Impurity specifications for critical materials in front-end processes need to be linked to known fault mechanisms so that economic viability of raw materials can be achieved.

• Detection of surface defects at ~0.5 x the minimum feature size for incoming materials and throughout the front end of the line (FEOL) is economically achievable with some continuous improvement through the 130-nm technology generation.

• Surface termination control will continue to drive requirements in isolation technology for FEOL processes.

• The greatest challenge facing front-end process defect inspection is the reliable, fast detection of partially etched contacts, missing/extra pattern local interconnects, and small residues in the bottom of vias and isolation trenches.

Lithography. Since deep ultraviolet (DUV) lithography will be a mainstream exposure technology for several technology generations, ammonia, amines, and other ambient base gas concentrations must be controlled so that photogenerated acids are not neutralized. To support this requirement, improved chemistry models; nonchemically activated DUV resists; and portable, easy-to-use, high-sensitivity detection tools must be developed along with standardized reference libraries of chemical spectra that can be used in comparisons with unknown samples.

Several other lithography-related DR issues present challenges for the industry. A reduction in backside particles must occur so that the focus budgets attributable to such particles can be optimized. As with other critical materials, there must be a better understanding of the impact of trace contaminants in photoresists on device yields, reliability, and performance as well as the ability to remove them during the resist-strip processes. Improved postdevelop inspections are necessary so that rapid yield learning and continuous yield improvement within photoprocessing can continue. Automated macroinspection capability (at the tens-of-microns level) on a per-wafer basis will aid in reducing photo rework and optimizing track/stepper performance for minimum defect contribution. Developments in novel defect-data analysis methods (spatial signature analysis, edge-die yield impact) will aid in the optimization of photoprocesses in order to achieve the lowest possible defect contribution. Finally, novel pellicle technology may be needed to help keep a lid on the cost of manufacturing defect-free masks.

Interconnect. Yield loss caused by contamination and field failures will continue to occur with higher frequency in the back end of the line (BEOL) than in all other manufacturing operations combined. Defect detection of the many interconnect failure modes will be critical for continuous yield learning. These modes include ultrasmall particles; scratches; bubbles, striations, cracking, and delamination in transparent dielectrics; pitting; corrosion and chemical etching in CMP; particles/residues in trenches and vias; and buried defects in complex layered films. One of the most challenging requirements for the implementation of advanced metallization techniques is effective posttrench and via etch cleans and subsequent surface preparation treatments. This facilitates nucleation layers for electroplated copper and CVD of silicides, barriers, and via/trench fills. Process chemistry regimes must be better understood so that the rate of residue buildup on chamber walls and subsequent flaking can be reduced, thus increasing mean time between cleanings. Fiber-optic monitors and other sensors must be developed and refined to alert operators to film buildup and incipient flaking conditions within CVD reactors and sputtering chambers.

Factory Integration. The development of sound DR strategies plays a pivotal role in meeting the goal of reduced costs and risks that is central to factory integration. Since yield losses result from excursions from the ideal process, engineers must understand how to prevent such excursions and to identify the process parameters that need to be controlled to achieve high yields. It is vitally important to determine the variation tolerance of critical process parameters as well as the interaction between processes that could lead to better process control and reduced reliance on end-of-line inspection. By using data from the threshold at which impurities in critical process fluids affect the process (etch rate, film uniformity) and device performance (threshold voltage, gate oxide integrity), in situ sensor development can be directed and the time it takes to reach high yield levels can be reduced by eliminating the defect sources in advance. Other DR issues highlighted in this portion of the roadmap include rapid yield ramp and factory performance metrics for reduced defects.

The Roadmap Series

The MICRO Mapping the Roadmap series will be presented over the course of 1998, with installments scheduled for the March, June, July/August, and October issues. In the yield model and defect budget (YMDB) installment in March, the Sematech 0.25-µm yield model, which was used to establish NTRS defect targets for the 250-nm technology node, will be described. This model is unique in the consortium’s yield-modeling experience because three member companies provided in-line defect and end-of-line yield data to help validate the model. There is a high degree of complexity in extrapolating defect targets to the unknown of future device designs and process flows. To deal with this complex problem, the YMDB subgroup developed a simple algorithm that accounts for both increasing process complexity and decreasing killer defect size. To support valid targets at future nodes, a great deal of yield model development will be necessary, especially in such areas as new defect mechanisms associated with damascene processing.

As noted above, defect detection (DD) is a critical component of any yield enhancement program. In the DD installment in June, the case will be made for refining DD technology requirements separately for each of the process R&D, yield ramp, and yield monitoring phases of manufacturing. The industry is beginning to understand this as recent developments among DD equipment suppliers show, and the roadmap highlights the need for closing the gap in both sensitivity at speed for line-monitoring applications and speed at sensitivity for yield ramp applications. Additionally, there will be a review of the need for continued emphasis on the development of sensors and detection technologies that operate as close as possible to the defect source, either in the processing environment during active processing or on the wafer housed within process equipment.

A new DR focus topic will be addressed in the defect sources and mechanisms (DSM) installment in July/August. This article will describe technology requirements for more rapid isolation and sourcing of faults, and the potential solutions that might bridge this gap in a much more complex environment of hundreds of millions of transistors and hundreds of processing steps. Topics will include statistical methods, fault isolation, invisible defects, and integrated yield analysis capabilities.

Traditional contamination control activity falls into the final focus topic—defect prevention and elimination (DPE). This installment, scheduled for October, will discuss technology requirements for process-critical materials (gases, chemicals, and the like), process equipment developments needed to meet future defect targets, and wafer environment control technology necessary to maintain ambients free of contamination that could cause defects and circuit faults. There will also be a review of opportunities for decreasing defects by continued developments in circuit design and better characterization of interactions between process steps.

Conclusion

This introduction to the Mapping the Roadmap series has attempted to provide a basis for the strong motivation to focus on defect reduction as a critical component of profitability within semiconductor manufacturing. The subsequent installments will provide background details and additional motivational thinking for the technology requirements published in the SIA roadmap as well as a more thorough review of the technology requirements themselves, the difficult challenges, and potential solutions within the four focus topic areas.

Acknowledgments

Portions of this article are adapted from The National Technology Roadmap for Semiconductors 1997 revision. Used with permission. A critical factor associated with progress since the 1994 roadmap revision has clearly been the interaction of numerous university, national lab, supplier, and end-user representatives. This article and certainly those to follow (not to mention the roadmap itself) would not be possible without such interaction. This cooperation clearly aided in leveling the effort among the participants, and also provided a very important forum in which numerous discussions yielded more credible information for the technology requirements and potential solutions.

We want to acknowledge the following DR CCTWG participants: Bob Blewer, Ken Tobin, Susan Cohen, Bill Fil, Venu Menon, Sanjiv Mittal, Milt Godwin, Ron Harris, Brian Duffy, Terry Francis, Farhang Shadman, Dan Hirleman, Daren Dance, Bill Fosnight, Keith Dillenbeck, Ralph Richardson, Zach Hatcher, Brian Trafas, Paul Proctor, Fred Lakhani, Randy Collica, Jim McAndrew, Mike Grobelny, Charlie Peterson, Jieh Hwa Shyu, Robert Alexander, Val Rio, Lindsey Hall, Pat Lamey, Matt Ivanis, Jennifer Sees, Bobby Bell, Chris Gondran, Dan Clark, Steve Lakeman, Devon Kinkead, Pat Gabella, Ram Akella, Hank Walker, Wojciech Maly, and Tom Larson. We would also like to acknowledge the following TWG advisory groups: Sematech’s Contamination Free Manufacturing FTAB as well as the consortium’s Defect Detection and Analysis and Defect Reduction in Equipment PTABs.

References

1. Van der Pol JA, Kuper FG, and Ooms ER, “Relation between Yield and Reliability of Integrated Circuits and Application to Failure Rate Assessment and Reduction in the One-Digit FIT and PPM Reliability Era,” Microelectronics Reliability, 36(11/12):1603—1610, 1996.

2. Puhakka R, and Hutcheson GD, “Analysis of Mature Fab Yields,” San Jose, CA, VLSI Research, October 1996.

3. “Change in Chip Making and How It Is Driving Process Diagnostics,” San Jose, CA, VLSI Research, June 1996.

4. The National Technology Roadmap for Semiconductors, San Jose, CA, SIA, 1997.

5. The National Technology Roadmap for Semiconductors, San Jose, CA, SIA, 1994.

David Jensen is program manager for defect reduction technology at Sematech, Austin, TX. He is an AMD assignee and while at the company, as a member of the technical staff, his primary responsibilities were for developing and deploying contamination-free manufacturing strategies. Before joining AMD, Jensen was at Digital Semiconductor for five years, where he was engineering supervisor of the Fab 6 CFM group. He served as cochair of the DR CCTWG for the 1997 revision of the SIA NTRS. Jensen holds a BS in mechanical engineering from Arizona State University (Tempe). (Jensen can be reached at 512/356-3756, or via E-mail, david.jensen@sematech.org.)

Charles Gross is senior engineering manager of Digital Semiconductor’s yield engineering group in Hudson, MA. He joined Digital’s semiconductor organization in 1987. His responsibilities have included engineering management in wafer fabrication and yield engineering. He also served as Fab 6 program manager from conception through start-up of the facility. Before joining Digital, Gross worked for RCA and Commodore Semiconductor. He has a BS in physics from Drexel University. (Gross can be reached at charles.gross@digital.com.)

Dinesh Mehta, PhD, is vp of administrative operations and strategic initiatives and member of the office of the chief executive at the Semiconductor Research Corp., Research Triangle Park, NC. He came to SRC in 1996 after a long career at AT&T with senior-executive-level assignments in R&D, engineering, manufacturing, and product management. He holds BE and MS degrees in mechanical engineering and MS and PhD degrees in material science. (Mehta can be reached at 919/941-9435, or via E-mail, mehta@src.org.)

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