Developing a condition-based process control model for STI trench depth control

Sreedhar Gaddam and Martin W. Braun, Texas Instruments

Shallow-trench isolation (STI), which is used to define active areas and to separate device elements in ICs, is critical for the proper functioning of transistors. The STI etch process is used to create shallow trenches in the silicon substrate, which are subsequently filled with dielectric material to form isolation barriers between device elements. Tight control of isolation critical dimension (CD) and trench depth is required for optimal device performance and for achieving desired yields. While STI CD variation degrades direct drain quiescent current (IDDQ), transistor performance, and speed, trench depth variation results in post-CMP step height variation, the erosion of active areas (moats), gate length reduction, incomplete isolation trench oxide fill and voids, IDDQ failures, and reduced wafer yields. To control STI CD and trench depth, effective and robust process control models and strategies are required, in addition to advanced processes and reliable metrology tools.

The standard STI etch process involves etching the bottom antireflective coating (BARC), the nitride, the underlying pad oxide, and a shallow trench into the silicon substrate. At the 130-nm technology node, STI etch uses a hard-mask process to reduce defectivity and improve chamber performance. In the first step of this process—nitride hard-mask open—the BARC, nitride, pad oxide, and some silicon are processed in the nitride etcher. In the next step, ex situ ash and wet cleans are performed. Following ashing and cleaning, wafers are processed in the silicon etcher to etch the remaining silicon trench. Because this process involves two separate etch steps, metrology can be performed after both nitride etch and silicon etch to achieve improved CD and trench depth monitoring and control. All metrology steps, including the measurement of CD, trench depth, and nitride thickness, are conducted using scatterometry.¹ Figure 1 presents a schematic view of the process flow.

Figure 1: Schematic flow diagram of the STI etch hard-mask process.

During etcher wet clean cycles, silicon etch rates tend to fall, resulting in a gradual downward shift in the total silicon trench depth. (Wet clean cycles are the periods between two wet clean events in the chamber. Hence, chamber radio frequency (RF) hours are zero immediately after a wet clean and reach their maximum value immediately before the next wet clean.) The downward trend in silicon etch depth causes lot-to-lot and tool-to-tool variations. Tool-to-tool variations occur when wet cleans are performed in different chambers at different times. Figure 2 illustrates the effect of a wet clean cycle on the trench depth.

Figure 2: Effect of performing an etcher wet clean on trench depth measurements.

Historically, engineers at Texas Instruments (TI; Dallas) have manually adjusted etch time on a regular basis to keep trench depth in control and on target. However, that tedious, non-value-added procedure requires that fab personnel constantly monitor trench depth using statistical process control charts. To eliminate the need for manual recipe management and reduce process variability, a fully automated feedback/feedforward process control strategy was designed and deployed in ProcessWorks, a TI-developed process control software application offered by Adventa Control Technologies (Plano, TX).

Control Model

To develop a control model for the software, simulation analysis was performed using Matlab (Natick, MA). The analysis enabled engineers to rapidly create prototypes of potential designs using historical data. The performance of several candidate models was evaluated based on overall performance statistics, ease of maintaining the control model, and visual inspection of the simulated performance in time-series representation. The model that performed best was selected for additional tuning and implementation.

The resulting control model takes into account variation caused by the nitride etcher, the silicon etcher, the reticle set, and the process type. Feedforward information includes postnitride-etch trench depth. The model automatically takes into account changes in the trench depth target specification. The final total silicon trench depth is fed back into the control model and used to update the model parameters. The process model employed in the control model is summarized in the following equation,

T_SD = (Etch Time X M) + B1 + B2 + T_SN

where Etch Time is the silicon main etch time, T_SD is the total silicon trench depth, T_SN is the silicon trench depth after nitride etch, and M, B1, and B2 are model parameters as defined in Table I. The process flow and control model are illustrated schematically in Figure 3.

Variable Name Type Partitioning M Model parameter (gain) SiMachine, process B1 Model parameter (offset) SetId, process B2 Model parameter (offset) SiNiMachine, process TSD Output/target — Etch Time Input — TSN Feedforward —

Table I: Variable definitions.

Figure 3: ProcessWorks model for STI etch trench depth control.

When a production lot is about to be processed in the silicon etcher, the controller automatically retrieves the model parameters that match the lot context, incorporates the target silicon trench depth (T_TSD) and post-nitride-etch trench depth (T_SN) from the manufacturing execution system, and then calculates the input to the etcher recipe (silicon main etch time). The etch time setting is subject to asymmetric maximum move constraints (i.e., it can decrease etch time more than it can increase it from one run to another).

After scatterometry has been performed on the post-silicon-etch wafers, the total silicon depth is uploaded to the controller. This measurement is checked against the goodness of fit, which defines the residual fit error of the scatterometry model when applied to the raw data. The final average trench depth measurement is also subject to a spike filter similar to those discussed in the literature.² The spike filter compares the current data to the most recent previous data to determine if they are gross outliers or if they represent a true process shift.

The metrology data are used to update the process gain M and the components of the process offsets B1 and B2. The exponentially weighted moving average (EWMA) observer is used to track the variation associated with each model parameter for the given lot context. Discussion of the properties of the EWMA observer is found in the literature.³ The EWMA observer for B1 is described in the following equation (the EWMA observer for B2 has the same form):

B1_(k+1) = B1_(k)– λ_B1X (T_TSD(k)– T_SD(k))

In this equation, the variable k denotes the current run, while k+1 denotes a future run. The variable λ_B1 is the tuning constant for the EWMA observer for the B1 parameter. B1 and B2 each have their own unique tuning parameter.

The EWMA observer for M is similar to that for B1. However, to take into account the dependence of etch rate on the wet clean cycle, a time-based tuning curve found in the literature was employed.⁴ This tuning curve determines the tuning constant λ_M and has the form:

This tuning curve is well suited for STI depth control, because it can be parameterized and fit to enable the control model to rapidly tune immediately following a wet clean event. Because post–wet clean metrology data are uncertain and it is difficult to know the RF hours immediately before lot processing, it is desirable to tune the controller rapidly when the etch rate in the wet clean cycle changes rapidly, rather than to make a full correction after the wet clean step. Figure 4 illustrates the properties of the tuning curve that make it suitable for this purpose.

In Figure 4, the variable φ₁ controls how fast the curve descends to the asymptotic value as RF hours (t) grow. The variable φ₂ determines the relative value of the initial and final values of the tuning curve as t grows. The variable φ₃ allows the overall curve to be scaled. The tuning parameters of the control model—λ_B1, λ_B2, φ₁, φ₂, and φ₃—were then optimized to provide the desired balance of robustness and performance. This operation was critical, since the process offset of the model is decomposed into B1 and B2. The literature demonstrates that the decomposition of model parameters, combined with EWMA observers, defies traditional assumptions of robust performance and stability bounds.⁵ Therefore, simulation on historical data ensured that the tuning parameters would work in the production environment.

Other possibilities exist to capture the ramplike nature of the etch rate's dependence on the wet clean cycle. The predictor-corrector control observer suggested in the literature is one such approach.⁶ Additionally, the Kalman filter or the recursive least-squares approach have been proposed for STI etch processes.⁷ While these methods are effective and applicable to a wide class of problems, the tuning curve proposed in this article provides a simple, effective method for matching the controller's response speed with the seasonality of the wet clean effect on the etch rate.

Implementation and Results

The control model was employed in the ProcessWorks advanced process control environment. After it was run in monitor mode for a period of time to validate the implementation and supporting automation code, the controller was released in control mode. Figure 5 illustrates the performance improvement that was achieved by using the controller. A comparison between Figures 2 and 5 demonstrates that the controller can control the wet etch process effectively.

Figure 5: Run time performance of the controller in production.

After a wet clean, look-ahead wafers are run for each process type performed in the tool. The data gained from this are fed directly into the controller and used by the EWMA filter and tuning curve to update the value of the process gain M for each tool/process combination. The controller can then maintain the trench depth target for the entire wet clean cycle.

The system offers several features for effective and robust process control. Two different spike filters (trench depth value and goodness of fit, both of which are derived from scatterometry data) are used to prevent bogus data from being supplied to the controller, and two different guard band settings (minimum/maximum bounds and run-to-run delta for etch time) are used to prevent out-of-bound conditions.

Conclusion

This article discusses the development and implementation of an etch chamber condition–based run-to-run process controller for use in STI trench depth control. The controller offers preventive maintenance cycle–based tuning and excursion protection. Its implementation has eliminated the need for manual process recipe adjustment and has improved process capability by approximately 30%. Actual process data before and after the controller was employed demonstrate its efficacy. The controller can effectively compensate for variations arising from wet clean cycles, tool/chamber matching, and process and reticle-set differences.

Acknowledgments

This article is an edited version of a paper presented at the IEEE/SEMI Advanced Semiconductor Manufacturing Conference, held April 11–12, 2005, in Munich. The authors would like to thank Stacy Bozarth, Padu Krishnagiri, Ulka Kumar, Don Sonom, James Yarborough, and John Bernard for helping to implement the STI etch trench depth controller at TI's Kilby Center (Dallas).

References

1. S Gaddam and C Baum, "An Improved Process, Metrology, and Methodology for Shallow Trench Isolation Etch," in Proceedings of the IEEE/SEMI Advanced Semiconductor Manufacturing Conference (Piscataway, NJ: IEEE, 2004), 93–97.

2. NS Patel and R Soper, "Control of Photolithography Alignment," in Run to Run Control in Semiconductor Manufacturing, chap. 16, ed. James Moyne, Enrique del Castillo, and Arnon M. Hurwitz (Boca Raton, FL: CRC Press, 2000), 249–260.

3. E del Castillo, Statistical Process Adjustment for Quality Control (New York: Wiley, 2002).

4. L Ljung and T Söderström, Theory and Practice of Recursive Identification (Cambridge, MA: MIT Press, 1983).

5. S Harrison et al., "An Evaluation of the Effects of Product Mix and Metrology Delay on the Performance of Segregated versus Threaded EWMA Control" (paper presented at the AEC/APC Symposium XV, Colorado Springs, CO, September 13–18, 2003).

6. S Butler et al., "Supervisory Run-to-Run Control of Polysilicon Gate Etch Using in Situ Ellipsometry," IEEE Transactions on Semiconductor Manufacturing 7, no. 2 (1994): 193–201.

7. R Chong et al., "Analysis of a Run-to-Run Controller on a Drifting STI Etch Process by Augmentation of the Integrated Interferometric Endpoint Detection System" (paper presented at the AEC/APC Symposium XIV, Snowbird, UT, September 7–12, 2002).

---

Sreedhar Gaddam is a senior process engineer and a group technical staff member at Texas Instruments' Kilby Center in Dallas. His responsibilities include process development; release to production and ramp to volume of STI etch processes; rapid thermal processing; and room-temperature vulcanizing of STI etch processes for the 130-, 90-, and 65-nm nodes. Previously, Gaddam was a senior process engineer at Unitrode/Texas Instruments and a process engineer at IDT. He received a BS in chemical engineering from Osmania University in Hyderabad, India, and an MS in chemical engineering from Arizona State University in Tempe. (Gaddam can be reached at 972/927-3096 or sreedhar_gaddam@ti.com.)

Martin W. Braun, PhD, works at Component Automation Systems, Intel, in Chandler, AZ. His responsibilities include research, development, and implementation of run-to-run control. He also focuses on real-time system identification and control and control-oriented approaches for inventory control and supply-chain management. In 2001, he joined Texas Instruments, where his responsibilities included run-to-run modeling and control of etch and photolithography processes. He received a BS from SUNY-Buffalo in Buffalo, NY, and MS and PhD degrees from Arizona State University in Tempe, all in chemical engineering. (Braun can be reached at 480/554-6339 or martin.w.braun@intel.com.)