Meeting the Nanoscale Device Fabrication Challenge

True, Integrated Design for Manufacturability Must be Implemented

Bijan Moslehi, PhD, is chief technology officer and senior vice president, semiconductor technology research, for The Noblemen Group, a boutique investment banking, strategic advisory, and business development firm. Moslehi has 20 years' experience working in the semiconductor and semiconductor equipment industries. He can be reached at bmoslehi@noblemengroup.com.

Over the past year, many chip manufacturers have introduced their 90-nm process technologies and ramp plans, and several have begun volume production. Crossing the 100-nm line marks the entry into nanometer-scale devices, a world where various second-order effects become major technology issues. These new challenges have started to dominate device behavior and have a negative impact on fabrication. A few of these problems have emerged as serious integration limiters, threatening to diminish the performance benefits that device scaling has provided up to this point.

The top technical challenge facing the development of sub-100-nm device and process technologies is power. Off-state device leakage, overall power consumption, and thermal heating have progressively and alarmingly increased with each new nanoscale CMOS technology node, a trend that will only continue to worsen. Poor device behaviors caused by heating and the subsequent temperature rise during chip operation accelerate circuit performance degradation. Other possible undesirable effects include shortened battery life and extra packaging and cooling costs.

Many attempts to address these problems result in fixes that significantly compromise performance. Recent high-profile and widely publicized cancellations or postponements of some high-performance products underscore the seriousness of these problems. It is clear that major innovations and new methodologies are urgently needed to overcome the leakage and power issues.

On the manufacturing front, the fabrication of nanoscale devices faces several important challenges, including process variabilities, narrowing process windows, and diminishing manufacturing tolerances that do not scale in step with the technology nodes. This combination of factors can increase the variability of device characteristics and circuit performance, resulting in lower yields. Such yield inhibitors include interconnect variabilities (caused by CMP dishing and erosion), critical dimension (CD) variations, and dopant fluctuations. As always, process engineers and equipment suppliers continue to work on major process and product innovations and offerings designed to attack these problems. For example, the recently introduced ECMP tools, based on electrochemical mechanical planarization technology, should alleviate many manufacturing problems associated with the copper CMP process.

As noted, the process community has traditionally addressed virtually all manufacturing issues. Consequently, design and process engineers have worked in isolated environments with minimal interaction; in most cases, designs have been "thrown over the wall" to manufacturing. In the sub-100-nm world, those days have to come to an end. All indications point to an inescapable fact: the process and fab teams are no longer able to address and solve certain critical variability issues on their own.

Process variabilities are often atomic-scale and statistical in nature, including process fluctuations that affect the threshold voltages of the transistors and line-edge roughness or CD variations that weaken device speed and performance. These effects require solid statistical physical models as well as integrated simulation and design software tools. Although advanced process control (APC) and other innovations have helped tighten the process windows and improve tolerances, the accepted manufacturing methods appear to be insufficient for addressing certain process variabilities and atomic-scale device fluctuations. New methodologies are required. The conventional approach of relying only on design rules (defined based on the capability of the manufacturing processes) and process specifications (established based on design requirements) needs to be overhauled to factor in these deleterious effects.

The main goals, though simple, are quite challenging. Nanoscale designs must be manufacturable with high yields in conventional wafer-fab environments and with minimum design respins. Furthermore, circuits must function properly and as intended during their typical operation under various realistic environmental conditions within a system. Ultimately, the shortest possible time-to-yield, time-to-market, and time-to-profits must be achieved with the lowest possible costs and targeted net-profit margins.

In response to these mounting challenges, the concept of design for manufacturability (DFM) has emerged as an absolute necessity. DFM goes beyond the earlier critical moves toward design-for-testability (DFT), a trend that has been evolving over the past few decades. For DFM to succeed, there must be a broad-based, integrated, and interdisciplinary approach, where process and design groups closely work together and fully understand the issues, constraints, and challenges of each other's domains. DFM requires cooperation and seamless interaction among design, process, and mask-shop engineers, which also implies that the long-established views on product and layout design, as well as design flow, must be significantly modified.

In the nanoscale regime, designers (and designs/circuits) must become process aware, while process engineers (and processes/manufacturing methods) have to be increasingly design and product aware. Robust layout and circuit designs must factor in those manufacturing variabilities that cannot be addressed by process, never losing sight of sound product design for yield (DFY) methodologies and goals. This approach links directly to overall costs and ultimate profits. DFM must provide optimized product designs, layouts, and design rules that are fully characterized on suitable representative structures for critical processes with optimized lithographic resolution enhancement techniques (RET). It must also factor in high yields and the desired margins in manufacturing, with minimum possible sensitivity to such critical parameters as CD, overlay, and process defects.

The semiconductor industry's experience with subwavelength lithography, where the use of various RET methods has enabled nanoscale technologies, serves as an interesting and relevant example. Several years ago when I worked at VLSI Technology, we started using optical proximity correction (OPC) techniques beyond the 180-nm node. Fortunately, we soon realized that the only way to succeed was to get the engineers from the design, lithography, mask, device, and module-integration groups to directly work together as a cohesive, functional team. We also collaborated very closely with the mask and OPC/design tool suppliers, effectively leveraging their knowledge, experience, and support. We also changed the design flow to reflect the paradigm shift in this iterative process. This exercise, a practical, hands-on introduction to DFM methods, proved to be quite successful.

DFM methodologies require the integration of design, process, and mask-making functions, something that may give many integrated device manufacturers (IDMs) an advantage. To effectively integrate these functions, the fabless and outsourced/contract manufacturing models need to be modified to strengthen partnerships and expand information sharing (including process, yield, and fab data) with customers throughout the design flow and across the supply chain. Whether in an IDM, fabless, or foundry setting, circuit and layout designers, process engineers and other fab groups, mask shops, electronic design automation tool providers, process equipment manufacturers, process control vendors, and factory automation suppliers all play critical roles and must collaborate with each other and with their customers.