When Matrix Semiconductor's founders decided their 3-D chip technology was ready to leave its Stanford University laboratory, they realized it needed help getting out the door to the process line. As it happened, some members of the Matrix process R&D team had worked for Cypress Semiconductor in San Jose. Established in 1984, the manufacturer has been offering its facilities as a developmental bridge for start-ups and university labs to get products to market.

R&D MIDWIFERY: Prototypes of Matrix Semiconductor's second-generation, monolithic, 3-D IC shown above were perfected at Cypress's SVTC. SEM PHOTO COURTESY OF MATRIX SEMICONDUCTOR

Now Matrix's low-cost 3-D memory chips—the first in the industry—are ready for use in handheld computers, mobile phones, and toys, including Mattel's new Juice Box personal media player. On November 8, the start-up announced that it had shipped 1 million ICs in just four months of volume production at TSMC.

Cypress, which specializes in a range of silicon-based products, formalized its midwife role in July 2004 by opening the Silicon Valley Technology Center (SVTC). The center gives clients such as Matrix and Mosel Vitelic access to 65-nm technology for advanced R&D. In late October, the facility completed the installation of an ASML Twinscan XT:1250 that features a numerical aperture of 0.85. Designed for sub-90-nm processes, the 193-nm scanner anchors an advanced lithography cell that also includes a photoresist coat-and-develop track tool as well as CD-SEM capability and overlay metrology.

Matrix is keen to credit the role Cypress has played in its success. The six-year-old firm used Cypress's silicon expertise and 16,000-sq-ft cleanroom to perfect its prototypes for high-volume manufacturing. In particular, the staff's ability to take care of wafer manufacturing and tool maintenance freed Matrix to focus on the design of its unique memory device.

"We started out doing the early R&D at the Stanford Nanofabrication Facility," recalls Dan Steere, vice president of sales and marketing for the Santa Clara, CA–based company. "It's good for doing early-stage work. We were able to do proof-of-concept work at Stanford, but we got to where we needed an advanced R&D fab for the next process in order to move torward volume production."

Steere says the Stanford-based team's search for a Bay Area R&D facility was made easier by the aforementioned team members from Cypress, which had been "letting people come in and rent equipment, time, and space in their R&D facility." He notes that Cypress is playing a supporting role in the evolution of the fabless business model. "When we started, it was very unusual for a fabless company to be doing significant process R&D. It's becoming more and more part of the future for fabless companies."

"A reasonably advanced R&D fab would have probably cost about $250 million," according to Matrix spokesman Phil Gomes. "We're fabless with a capital 'F.'" An important element of this evolution is the disposition of fab-related IP, "because when you're making three-dimensional integrated circuits, the design and the process are very closely intertwined."

"People are coming up with creative ways to build new products...so you need a facility like Cypress's Silicon Valley Technology Center to be able to do that," Steere adds. "That's a business model that's going to become more common in the fabless industry."

Jodi Shelton, executive director of the Fabless Semiconductor Association, agrees that the business model is evolving. Increasingly complex technology requires the association's members to conduct extensive R&D in order to maximize their relationships with foundries, she notes. Collaboration between fabless firms and foundries will continue to grow significantly. In addition to Matrix's special foundry relationships necessitated by its unique, value-added process requirements, Shelton points to partnerships based on advanced technology such as the one between Xilinx and UMC.

Bert Bruggeman, SVTC's managing director, says the center essentially is "a Cypress R&D fabrication line in San Jose" that the company has been renting to "third-party engineering groups." The outside parties use the equipment, software, and other infrastructure capabilities "to develop their silicon-based technologies," without needing to invest in bricks, mortar, and tools.

In 2000 Mosel Vitelic became the first resident customer to use Cypress and its newly installed 200-mm process technology. Cypress opened in 1984 with a 5-in. wafer fab and a qualified 1.2-µm, 1-Kb SRAM. A Cypress MRAM subsidiary took up residence as the second customer in 2001. Matrix exhausted the developmental possibilities of its 4-in. wafer line at Stanford before coming to Cypress in 2002, says Bruggeman. He cites the start-up as probably the best illustration of how SVTC is trying to position itself as a "bridge between the lab and the fab."

Matrix crossed the bridge in approximately a year and a half to prepare its technology for transfer to Taiwan, explains Bruggeman. "We don't do manufacturing. We also don't do basic research. We're basically a small 'r,' big 'D' environment where people come in and put their engineers on-site. They get trained, they get certified. It's like they're working in their own R&D fab without having to build it and put equipment in it and having to manage it."

SVTC claims to be the first R&D services provider to offer 65-nm process capabilities. Bruggeman says the newly installed ASML-based lithography cell enables the center to keep pace with the tech-node forecasts in the International Technology Roadmap for Semiconductors. The center's extensive toolset spans the range of process, metrology, and failure-analysis gear, including Novellus PECVD oxide equipment, FSI cleaning systems, KLA-Tencor defect tools, and Hitachi SEMs.

Given its 65-nm process capability, SVTC offers advanced defect-metrology technology by definition, Bruggeman points out. "As part of our developing technology, we are trying to identify failure modes. We're asking, 'What are the yield failure modes, and do you have the right equipment to detect them? That's a more advanced type of application, where you're trying to make something functional—whether it's electrically, optically, or mechanically—on silicon."

Steere says the Matrix high-rise devices present no unique defect issues. "In general, the types of defects we run into are similar to the types of defects that any other silicon-based process sees."

SVTC works mainly with silicon-based technology, and it can accommodate MEMS, photonics, and nanotech applications. In all these different segments "the overriding factor is that people are trying to bring new value to the silicon base by using the capital equipment available," Bruggeman says.

The center's managing director believes a wry comment by one of Matrix's cofounders encapsulates the silicon-only dictum. Thomas Lee, a professor of electrical engineering at Stanford, insisted that "no new atoms" were needed to develop the 3-D device. In other words, Bruggeman explains, "please use what's available in traditional semiconductor lines." Working within the proven capabilities of standard silicon processes not only keeps costs down, it also limits the headaches that can arise when trying to introduce relatively unknown techniques and materials into a volume-production setting.

"You can see that as either a limitation or an advantage of SVTC," Bruggeman says. The approach means that early in the R&D phase, one is forced in a sense to design devices and develop processes "around that more-standard infrastructure. So at the end of the day, when you have to transfer to manufacturing you don't find out that this is a really weird material that doesn't fit in the fab."

Matrix's Steere believes "using what's available" was the only route to take. "We understood that if we want to be able to take advantage of the existing infrastructure and ongoing innovation, we need to stick to [traditional] tools and materials. Any time you bring new materials into a fab, that's a very expensive proposition."

Aside from the boost to the bottom line, Cypress benefits in other ways. The revenue helps to offset its own R&D costs. Bruggeman notes another key benefit: "It's also a vehicle for us to keep an eye on future partners. Once in a while when we run into a company, there will be more to our relationship than just a pay-for-rent agreement. Those strategic opportunities can then add to Cypress's technology and product portfolio."

Matrix led all other fabless firms in 2003 fund-raising, according to FSA. Investors pumped $52 million into the start-up last year. The company is offering the 3-D device in standard packaging and in a multimedia card with 64-, 32-, and 16-Mb capacities.

"We're a different way of thinking about fabless," Matrix's Gomes points out. "A more traditional fabless company...would advance the design and then import that design to a somewhat generic process. In our case, we hold the design IP, the process IP. And in developing the process IP, we use the equipment over at Cypress to perfect those recipes before we transfer the process to TSMC."

Needless to say, guarding those "recipes" ranks high on Matrix's to-do list, as it does, of course, with all chipmakers—billion-dollar fab or no billion-dollar fab. "Obviously, that's very important to us," Steere says. "We have over 85 patents. It's very important to have very strong safeguards."

The sales and marketing director says the company viewed the developmental path it took "as necessary from the beginning. Then the question was, did we choose the right partners?" He calls Matrix's relationships with Cypress and TSMC "excellent."

The executive might also be able to use the same adjective to describe Matrix's bottom line after the upcoming holiday season. That's when the 3-D memory chip may find itself under Christmas trees and inside the cartridges for Mattel's Juice Box toy.—JC