INDUSTRY NEWS

SIA seeks study help

The Semiconductor Industry Association has requested proposals from public and private institutions that are interested in conducting an independent retrospective epidemiological study of U.S. wafer fab workers. The announcement follows a feasibility study authorized by SIA's scientific advisory committee that was completed in March by Johns Hopkins University Bloomberg School of Public Health. The study concluded that sufficient records exist to conduct a scientifically valid inquiry.

"The SIA study will be one of the largest industry-sponsored epidemiological studies ever undertaken," said association president George Scalise. "[It] will review data on more than 200,000 people who worked in U.S. semiconductor manufacturing facilities from the late 1960s to the present time in an effort to determine whether there is an increased risk of cancer related to working in such facilities."

Potential investigators must submit an expression of interest and statement of qualifications to conduct a retrospective investigation. Those submissions must be informed by the analysis of potential study designs provided by the Johns Hopkins researchers. The focus is on several areas: a comparison of the cancer risk and all-causes mortality for workers in the IC industry and the U.S. population; a comparison of the cancer risk and all-causes mortality for fab workers, nonfab workers, and the U.S. population; and the identification of subgroups of fab workers who have been exposed to varying levels of chemicals and hazardous materials, a comparison of risk among subgroups, and a comparison between such fab workers and nonfab workers.

SIA says it hopes to select a research team by 1Q2005. The Johns Hopkins team estimates that the proposed study, which will be funded by association members, will take 3–5 years. (For more on the background of this study, see "SIA backs fab cancer study critics have long demanded" in the Industry News section in MICRO's May 2004 issue.)

TEL, LETI collaborate

A major semiconductor equipment supplier and research consortium have joined together to develop next-generation front-end-of-line CMOS process technology. Tokyo Electron and CEA LETI, the French R&D center, have agreed to study new materials that will be needed to meet 45-nm and below gate-stack challenges. The main focus of the FEOL partnership, based at LETI's Nanotec300 facility in Grenoble, will be on high-k dielectrics and metal-gate films as well as associated pre- and postprocess steps. TEL will provide flexible-batch and single-wafer thermal processing systems; the single-wafer tool will be outfitted with a chamber devoted to surface treatment of the materials and another chamber will handle metal processes. The partners say that aggressive electrical and integration performance milestones have already been targeted for 2004 and 2005.

Flexible display R&D funded

A North Carolina hardware development company and a pair of university researchers have received a nearly $5 million award to develop a plasma source for flexible-display manufacturing applications. The U.S. Display Consortium (USDC) has funded an R&D project led by Sencera in conjunction with its academic partners—Francis Chen of the University of California at Los Angeles and George Tynan of the University of California at San Diego—to build a source capable of depositing high-quality gate dielectrics at temperatures at or below 100°C on plastic substrates. Once it is built, the plasma unit will be installed on a commercially available tool, and a process will be developed for use in the fabrication of electronic display backplanes. The deposition source will eventually be integrated into a tool at the newly established Flexible Display Center, located at the old Motorola flat-panel display plant at Arizona State University. The USDC R&D program is a collaborative effort of the U.S. Army Research Lab and private industry.

Trikon lands MRAM funds

The U.K. Department of Trade and Industry has awarded nearly $3 million to Trikon Technologies to help fund the development of broad ion beam deposition (BIBD) technology for magnetoresistive random-access memory (MRAM) manufacturing. The company says BIBD offers significant benefits over magnetron sputtering because the high-vacuum process controls ion energy and flux independently to maintain critical film properties. The project will result in a 300-mm BIBD tool capable of fabricating full stacks and insulator layers. The grant is part of the UK's Micro and Nanotechnology Manufacturing Initiative, launched in 2003.

CMOS alternative advances

Process capability at the 45-nm technology node has been demonstrated for a multigate field-effect transistor (MuGFET), a potential replacement for conventional CMOS transistors. The work was done as part of a custom development program at ATDF (the R&D center recently spun off from Sematech), HPL Technologies, and a combination of a device maker, a university, and several equipment and materials suppliers. HPL delivered a test chip that uses a new device topology and special analog device design considerations. The chip is available from ATDF for any company that needs access to this emerging process technology. The development facility says the demonstration marks the completion of the first phase of efforts to identify manufacturing problems associated with MuGFET fabrication on silicon.