INDUSTRY NEWS

SILICON NANOELECTRONICS:
New report examines challenges of CMOS extension and beyond

The post-CMOS world of device manufacturing holds great promise and poses many challenges. A nanoscale world that boasts spin logic, quantum cellular automata, and molecular devices presents the semiconductor industry with formidable long-term obstacles.

CHAINS AND WIRES: False-color TEM images of self-assembled gold nano- chains and silver (shown as blue-gray here) nanowires. IMAGES COURTESY OF HEINRICH JAEGER AND WARD LOPES, UNIVERSITY OF CHICAGO

A new joint report by the National Nanotechnology Initiative (NNI) and the Semiconductor Research Corp. (SRC) details the nature and extent of those hurdles. Published in August, Silicon Nanoelectronics and Beyond: Challenges and Research Directions notes that the semiconductor industry "faces the twin challenges of extending charge-based electronics to its ultimate limits while simultaneously inventing new information-processing technologies that can support continued exponential improvements in performance and cost." This capability must extend, the authors point out, for several decades "beyond the end of scaling projected by the International Technology Roadmap for Semiconductors."

Officially a first draft, the 39-page report is based on the work of a joint board formed by the two organizations. The board was asked to examine the role of research by both NNI and industry and then make recommendations for future research.

Five consultative working groups established by the board focused on key research requirements for five areas of concern. Those corresponding chapters cover post-CMOS information processing technologies; the status of novel materials and assembly methods for extending charge-based technology to its ultimate limit; multiscale, multiphenomena modeling and simulation; novel nanoarchitectures; and nano–environmental, safety, and health (ESH) issues.

Overall progress requires that each of those focus areas work in concert with the others. For example, are chipmakers working with equipment manufacturers to address the need for accurate characterization techniques? "This report looks much further out," replies Stefan Zollner, an engineer in Freescale Semiconductor's Advanced Products Research and Development Lab and a participant in the novel materials group. Semiconductor manufacturers and toolmakers are collaborating "to look at novel characterization methods." However, he emphasizes, "in my view the purpose of the report is to influence the Scientific and Technology Policy of the United States [document]."

Broad in scope, the report doesn't directly address yields and defects. "I think the question is whether there is a fundamental theorem that yields will go down as materials become more complex," notes Zollner. "So far, we haven't really reached stages yet where we have done things to our materials. I know we have introduced copper and low-k materials, and you have a track record showing whether yields are affected by the introduction of these two materials." He points out, however, "As we're looking forward to bringing in nanoparticles, nanomaterials, and nanolaminates, there is just so much that can go wrong. Therefore, you would think that you'd need more metrology and more process control."

In the modeling and simulation chapter, the working group makes it clear that developing advanced tools is crucial for making multiscale, multiphenomena nanoscale devices. A key challenge for designing nanoscale devices is maintaining those capabilities that make traditional CMOS equipment effective while "leveraging radically new (and not yet fully understood) properties of new technologies."

Harold Hosack believes that nanoscale design and processing "have many challenges that distinguish them from standard IC manufacturing. The overarching challenge, however, is that they require a fundamentally different view of the world of technology."

The director of interconnect and packaging sciences at SRC, Hosack says chipmakers have used modeling and simulation "to very good advantage." He notes that no "new" physics are involved in the nanoregime. However, modeling at the "atomistic level" presents unique challenges to include physical effects that have not been important at larger scales. "In the past, a lot of the modeling has been done at a level very small compared with people's normal senses, but it has been large enough that we could use statistical concepts.

"As we go to a nanoscale regime we're coming to a point where . . . we have to look at building things from the atomic level. Many of the problems are—I wouldn't say much larger—but they're different. You can't use things like effective mass, which is a very powerful tool we use in modeling many semiconductor devices. We talk about band structure in silicon and metals, which is almost a macroscopic phenomenon compared with the nanoscale." At the nanoscale, "there are simply a lot more parameters to worry about."

Are these problems solvable? "In principle they're all solvable," Hosack replies. "We think we have most of the questions, and we understand most of the fundamental physics, starting from quantum mechanics." Ultimately, the answer "has to do with cost and it has to do with the magnitude of the problem. For example, people at the national labs have been working very hard for many years to try to build up the capacity to model behavior of a few thousand atoms put together. That is a very hard problem from the standpoint of requiring tremendous computational capability. Many of the people at the national labs have some of the world's most powerful computational systems, and even they're limited in terms of what they can do."

Because innumerable atoms will be interacting, "now you're talking about things that you want to model on both the atomistic scale and at the macroscale," continues Hosack. These "fundamentally different scale regimes" involve computer models with a very large number of parameters and large grid networks. "Those are difficult because you have to be able to put in the right physics and do the computations."

The report notes the fundamental changes that are required to extend beyond silicon CMOS. In particular, it identifies the need for new materials that enable devices to "store and manipulate computational state arrays." These functional materials include crystalline superlattice structures with embedded nanocrystals, quantum dots, and photonic cavities. Another potential post-CMOS concept involves epitaxially layered materials, in which each layer is patterned and doped in order to function in a specific and unique manner. "The unifying concept is that the device functionality will be achieved by quantum interactions between atoms confined in a unit cell of a lattice," according to the authors.

Kang Wang is director of Functional Engineered Nano Architectonics at Microelectronics Advanced Research Corp. (MARCO) and a professor in the electrical engineering department at the University of California at Los Angeles. A member of both the materials and post-CMOS working groups, Wang says MARCO has been looking for a top-down vision to go beyond the limitations of scaled devices. The criteria set forth by the SIA through SRC and NNI entails working from the bottom to explore materials and new fabrication methods, such as self-assembly, in order to eventually devise "the functional blocks which are called nanoarchitecture."

An important question is how to "resolve the issue of scaled devices," Wang notes. "This includes low current drive, power dissipation per unit area, and reproducible manufacturing at low cost. How can you put all these pieces together?" He compares the technological feat with "putting nano-Legos together." The working group is examining approaches from the atomic and molecular levels with new materials.

The relation of materials and ESH looms large. The report emphasizes the need for nanotechnology ESH research to extend CMOS technology. More importantly, it stresses that much more nano-ESH research will be required on a broad range of materials. The draft calls for "significant work" to establish an infrastructure to "monitor nanoparticles, characterize nanoparticle toxicology, exposure paths and bio-persistence, and disseminate the information." Crucially, the ESH results and risk assessments should be shared with the nanotechnology researchers "using terminology and nomenclature that will help them translate the risk to new materials that they may be studying, so they can use safe handling procedures."

In addition, the nano-ESH working group's chapter emphasizes the need to share research results with the public and press "in a way that explains the potential hazards and risks of these new materials." Research into real-time metrology methods for nanoparticles in both air and liquids is a particularly crucial need, the authors note.

Given the broad range of materials over the CMOS-era horizon, the working group proposes that government agencies such as EPA, the National Institutes of Health, and the National Institute for Occupational Safety and Health fund research that will foster understanding of the potential risks involved in handling and disposal of the materials. The group points out that even though the intrinsic ESH properties of nanomaterials may be understood, this knowledge "may or may not be consistent with in situ behavior in wafer fabrication unit processes. Recombination, destruction, aggregation, chemical and physical alternation, and so on may all occur, depending upon the process use and tool conditions."

Freescale's Zollner says his interest in the research draft paper flows from his involvement with the National Science Foundation in forming the first six nanoscale scientific engineering centers. The grand themes of his working group are emerging research materials and nanoscale characterization methods. The latter is Zollner's particular area of interest.

The chapter successfully identifies the knowledge gaps the industry needs to fill in order to successfully develop nanofabrication techniques, he believes. "It talks about the complexity of nanolaminates where you have, let's say, two metal oxide materials together and you have a native oxide under a hafnium oxide high-k material. Because of the treatment of your oxide, you might have compositional gradients. It would be nice if we could make more precise measurements, but we cannot."

The chapter notes that pattern formation solutions for atomic-scale dimensional control are needed. Directed self-assembly is mentioned as one potential option for affordable fabrication. Zollner suggests that lithography will be used to "sort of scratch the surface, and then you will see growth that is not going to produce a complete layer. It will be somewhat of a selective growth, where you deposit material near the area that you've prepared.

"In a way, you already see this on the market," he continues. "For instance, you can etch divots in the source drain, and you can grow silicon germanium or some other material selectively." Zollner's definition of self-assembly "means you locally influence the surface conditions, and then you therefore encourage growth in a particular area." He acknowledges that his definition may differ from others. "We have always dealt with self-alignment. For example, a silicide formation is self-aligned. The example I've described with selective epitaxy in the source drain region to influence stress in the channel—I think we're already on our way to self-assembly, and it's going to be a continuous transition where we see more and more of that."—JC