Defect/Yield Analysis and Metrology

Using an E-beam method and line monitoring to perform in-line inspection

Stéphanie Desmercieres and Gilles Roy, Altis Semiconductor;
and Pierre Lefebvre, KLA-Tencor

The complexity of advanced wafer processes has increased the risk of unique defects such as buried electrical defects and optically transparent residues. Using its existing inspection toolset, Altis Semiconductor (an IBM-Infineon joint venture in Corbeil-Essonnes, France) was unable to detect such defects before final test, risking yield losses. To support its yield-ramp and yield-monitoring strategies, the company turned to E-beam inspection (EBI). With its unique voltage contrast inspection capability, EBI can ensure that critical (killer) defects are detected before the end of line, resulting in considerable cost savings and increasing learning cycles during technology ramps.

Altis installed its first EBI tool, an eS20XP from KLA-Tencor (San Jose), in April 2001. The system was used in engineering analysis and line-monitoring applications to monitor production lots in-line, enabling the company to react more effectively to process changes and defect excursions.

This article demonstrates that EBI has been key to optimal yield improvement and monitoring on Altis's copper logic production line. By using the technology, the fab's yield management team was able to identify and monitor buried electrical defects in-line. In addition, the article discusses the requirements for implementing EBI in order to perform volume production monitoring. Three case studies show how EBI was used to characterize and monitor buried electrical defects and defects that could not be detected in-line using conventional optical inspection. In all three cases, EBI resulted in yield-improvement cycles that were three to six weeks faster than those achieved using traditional methodologies that depend on in-line and final test results.

From Engineering Analysis to Line-Monitoring Applications

Inspection requirements and toolsets vary from the product ramp phase to production. During ramps, the line must be highly sensitive to all defect types, since priority is placed on characterizing defects in preparation for line monitoring. Bright-field and EBI inspection technologies provide the required sensitivity.

EBI is used in an engineering mode to identify critical process layers, perform systematic scanning electron microscopy (SEM) defect review, characterize critical defect types through failure analysis, and correlate defects with final wafer test to determine their electrical impact. The E-beam tool's contrast binning is augmented by in-line automated defect classification (iADC) to provide quick, accurate defect classification.

Once yield has been brought up to production levels, the focus shifts to monitoring the line for yield-impacting defect excursions. A larger array of inspection technologies—including dark-field inspection, blanket checks, bright-field inspection, and EBI—is used during production than during product ramps. During the product-monitoring phase, EBI is employed to detect defect excursions caused by process or tool drifts. When an excursion is detected, the offending tool is stopped. Analysis is performed to identify the problem, an action plan is defined, and the tool is restarted when the problem has been resolved.

Steps for Implementing EBI Line Monitoring

Before Altis established EBI as part of its line-monitoring strategy, engineers spent time learning about the tool's capabilities. Not only did they become proficient at creating effective inspection setups, but they also used characterization and failure analysis at final wafer test to study the defect types that they were detecting. To optimize EBI in production, the fab defined and implemented a strategy for throughput, stability, and defect review. In addition, it devised a sampling plan as a function of tool capacity and lot cycle time.

Throughput. During the engineering phase, the target throughput was defined as 50 wafers per week. This target was based on estimated wafer inspection time (a function of inspection setup parameters) and available engineering time (8 hours a day). The iADC feature was used to minimize review time and improve throughput. In addition, the inspection setup was modified to concentrate on the failed area of the die. After the inspection care area, pixel size, and sample plan were modified, throughput was improved by 50%, resulting in a final throughput of 75 wafers per week.

Inspection setups are typically a compromise between lot cycle time, setup parameters, review, and sampling strategy. While engineering usually requests that the entire wafer be inspected, the resulting lot cycle time often renders that impractical. Sampling strategies are derived based on the inspection goal, the requested areas to be inspected, and the resulting throughput. In some cases, requests from the process integration team can be fulfilled. However, care areas and/or sample plans have to be readjusted most of the time to achieve an acceptable throughput (1 to 1.5 hours per wafer) while maintaining meaningful line monitoring. Meaningful line monitoring includes finding defects of interest and their wafer signatures. Additionally, over a period of time, Altis implemented software upgrades to improve factory automation integration and flexibility during production.

Stability. Monitoring the line and identifying defect excursions reliably to stop the right tool at the right time depends on a stable defect baseline. The robustness of the inspection setup as well as the reliability and stability of the inspection tool are critical to establishing a stable baseline. To create a robust inspection regimen at Altis, setup parameters were optimized to achieve a high capture rate for the defect of interest, while an acceptable nuisance rate was maintained. Because of baseline issues, critical tool parameters were monitored to ensure tool stability. Weekly equipment preventive maintenance was modified to include the monitoring of the beam current, aperture current, and spot size. As a result of these measures, the baseline was stabilized and a procedure was put in place for maintaining reliable trend charts.

Defect-Review Strategy. The quality and speed of defect classification significantly affects the effectiveness of in-line monitoring inspection. The implementation of iADC improved classification accuracy and maximized tool utilization and throughput. Those improvements, in turn, guaranteed the availability of faster, more-accurate information on killer defects of interest and, therefore, better monitoring capability.

The E-beam tool uses contrast binning to classify defects as either bright or dark. While useful, this breakdown does not provide enough information to classify defects on some layers. As shown in Figure 1, iADC can distinguish between cheezing, corrosion, dark, bright, and physical defects such as surface particles, increasing the number of classification categories from two to five or six. In addition, it automatically transfers an image patch grabbed during inspection to the yield management system, where it can be reviewed at any time. The system's off-line review capacity is faster than on-line review, improving lot cycle times and inspection tool capacity.

EBI Inspection Paretos. Line-monitoring sampling is a function of tool capacity and lot cycle times. Altis dedicated 79% of its EBI to line monitoring and 21% to new products engineering. It focused 77% of inspections on 0.18-µm copper technology, 16% on 0.13-µm copper technology, and 7% on 0.22-µm aluminum technology. In the 0.18-µm area, inspections focused on the post-tungsten CMP contact and metal layers, as illustrated in Figure 2.

Figure 2: (a) Technologies and technology nodes, and (b) layers inspected using the E-beam tool at Altis.

Baseline Yield Improvement and Excursion Control

The implementation of EBI in-line monitoring has repeatedly reduced the time necessary to identify and resolve critical yield issues by 3 to 6 weeks. Three examples of how this was achieved are presented here.

SRAM Design. In a posttungsten CMP contact process used to manufacture SRAM designs, EBI was first used in engineering mode to detect a critical electrical defect. Failure analysis identified this defect, seen by the tool as a dark contact, as an open contact. By overlaying EBI inspection maps with maps from final wafer test, it was determined that 80% of the open contacts were killer defects. The remaining 20% were physical nonkiller defects such as surface particles. EBI, with its voltage contrast capability, can flag such electrical defects in-line.

Following this step, yield-excursion monitoring was implemented, allowing the investigators to rapidly identify the root cause of the excursion. Focused ion beam (FIB) analysis revealed several root causes, including a contamination issue that was later determined to be caused by an incomplete etch-chamber clean and a photo/etch issue that was caused by micromasking on reticles. Figure 3 presents SEM and FIB images of the open contacts. Figure 4 shows the EBI defect-yield trend chart for three contact etch chambers. Numerous excursions occurred over the study period. In each case, the in-line EBI monitor enabled the fab to detect the excursion and take corrective measures approximately six weeks earlier than if they had relied on final test.

Figure 4: EBI defect-yield trend chart for three contact etch chambers. Yields declined as a result of tool maintenance, micromasking on reticles, and an incomplete etch-chamber clean.

EDRAM Design. In another posttungsten contact CMP process, final product test results indicated that EDRAM contact failures were much higher than the reference SRAM contact failures for the same die. Altis used EBI to verify these results. The failure rate was calculated as the total count of dark defects divided by the total count of scanned contacts. EBI results showed that EDRAM failure rates, on average, were 3.7 times the failure rate of the SRAM design, confirming what was observed at final test.

The fab then used EBI to analyze the contact failure rates of two other products. On these products, the failure rates of the SRAMs were only 25 and 50% of that on the reference SRAM. Based on this analysis, the fab decided to install an EBI monitor for the EDRAM design. By using EBI monitoring to achieve process improvements, the EDRAM failure rate, on average, was reduced to 1.2 times the failure rate of the reference SRAM design. As can be seen in Figure 5, EBI results correlated with final wafer test results, and the new process produced much more stable results than the old process. Once again, EBI monitoring enabled the fab to realize yield improvements six weeks earlier than if they had relied on final test to drive process improvements.

Logic Design. In the third case, the fab identified a shortcoming in its ability to monitor the logic metal 3 postliner CMP process. Both in-line test and optical defect density monitors failed to detect a yield crisis that was only visible at final wafer test. Failure analysis revealed the source of the yield problem to be a liner residue that caused a metal 3 short. Figures 6a–6c show a top view, cross section, and postcopper strip view of the defect.

Once the defect type was understood, it became clear why existing monitoring had been ineffective. As can be seen in Figure 6, the liner defect, while visible in the SEM images, was transparent when viewed optically. Hence, optical inspection (Figure 6d) had been unable to detect the defect. The liner residue was also specific to the product structure, so that it could not be detected through in-line tests. In order to detect the defect in-line, an EBI monitor was required, resulting in the image in Figure 6e. For monitoring efficiency, iADC was used to filter and bin the defect types, and then SEM review was used to verify the classification of the liner residue.

Using that methodology, Altis evaluated two process changes. The first, a modification of overpolish time during postliner CMP, had little effect on the number of liner shorts. The second, the use of a new slurry at postoxide CMP, proved to be the solution, eliminating the liner shorts completely. In this case, EBI monitoring resolved the issue three weeks faster than did wafer final test.

Conclusion

Altis has shown that EBI monitoring is key to effective yield improvement and excursion monitoring, leading to tight process and tool control in its copper logic volume-production line. Successful sampling strategies allowed the company to compromise between the desire to inspect the full wafer and lot cycle-time constraints.

Three case studies illustrated the benefits of using EBI, contrast binning, and iADC to perform line monitoring. EBI was used to characterize and monitor critical defects on product wafers in-line that otherwise would have been detectable only at wafer final test. Detecting those defects in-line enabled the company to take corrective actions sooner than would have been the case had it relied on final wafer test results.

Acknowledgments

The authors would like to thank several colleagues at Altis Semiconductor for their involvement in the EBI studies and the implementation of EBI line-monitoring procedures: Philippe Bertin, defect density engineer; Sylvie Schon, technical leader; Jean-Luc Baltzinger, defect density engineer; Matthias Bostelmann, yield engineering; Michele Mercier, failure analysis; Jean-Yves Nots, yield engineering; and Francesco Castelli, equipment engineer.

Stéphanie Desmercieres is a defect density engineer at Altis Semiconductor's manufacturing site in Corbeil-Essonnes, France. She has been with the company since 2001. She received an MS in surface analysis technology from the University of Orsay, Paris, in 1999. (Desmercieres can be reached at +33 60 900207 or stephanie.desmercieres@altissemiconductor.com.)

Gilles Roy is the defectivity and line-monitoring manager at Altis Semiconductor's manufacturing site, a position he has held since 1999. He has filled several leading positions at the facility for 20 years. In addition, he has been in operations and engineering management at IBM, IBM/Siemens, and IBM/Toshiba. He received an engineering degree from the Centre d'Etudes Supérieures Industrielles in Paris in 1993. (Roy can be reached at +33 60 885226 or gilles.roy@altissemiconductor.com.)

Pierre Lefebvre, PhD, joined KLA-Tencor (San Jose) as an applications engineer in 1998. He has worked in several defect inspection areas, including bright-field and E-beam technology. He received a diploma from the Chemical Engineering School in Lyon, France, in 1993 and a PhD in physical chemistry from the University of North Carolina at Chapel Hill in 1997. (Lefebvre can be reached at +65 9832 5402 or pierre.lefebvre@kla-tencor.com.)