Intel ramps up EUV litho development, installs
300-mm microexposure system, sets up
photomask pilot line

Extreme-ultraviolet (EUV) lithography has entered the development phase at Intel. The company said in early August that it had installed the first commercial microexposure tool (MET) at its RP1 fab in Hillsboro, OR, and established an EUV photomask pilot line at its Santa Clara, CA, mask house.

EXTREMELY UPBEAT: Program manager Melissa Shell (shown here with EUV tool) says she's encouraged by early test-wafer results. PHOTO COURTESY OF INTEL

"We are making progress toward implementing EUV lithography technology in manufacturing with the 32-nm process in 2009," said Ken David, Intel's director of components research for its technology and manufacturing group. The 2009 insertion point for EUV at 32 nm puts Intel some 4 years ahead of the 2013 node set in the most recent edition of the International Technology Roadmap for Semiconductors.

The MET, manufactured by Exitech (Oxford, UK), has a field size of 600 X 600 µm and can print 30-nm features. The 300-mm system is integrated with a TEL photoresist track tool, which will allow Intel to develop EUV resists and examine the impact of mask defectivity. The mask pilot line features a commercial EUV maskmaking tool, an E-beam mask repair tool, and a mask-blank defect-inspection tool, with plans for more EUV-specific equipment to be brought in during the next two years. Intel says it will produce EUV masks internally.

When Melissa Shell, Intel's program manager for EUVL research, spoke to MICRO about the project in late September, the first test wafers had already been processed. "We've printed several wafers that are being primarily used for tool qualification and acceptance testing, checking out the optics, making sure they're good, finding best focus. (We're) doing all the things one normally does when qualifying a new stepper. We've run several wafers and so far things are looking pretty encouraging."

When asked about the resist-processing tool, Shell said "it's a production-type TEL track; we do have some features incorporated into it that are options that TEL has offered but we've just never used at Intel. Like hand dispense, because we want to be able to plumb very small quantities of resists when we're doing resist testing.

"We've got extra facilities put in for doing different types of waste treatment because we're not entirely sure what chemistry is going to be the optimal chemistry used in EUV. We know what we're using now, what the starting platforms are, and they're very close to conventional DUV resists. But looking into the future, we could conceive of doing something different and we would want to have the track plumbed to be able to deal with that."

As far as the areas of overlap and difference between existing lithographic techniques and EUV, Shell sees the new technology as "an extension of optical scaling.... All of the tricks that one uses to be able to play with k factors and how you optimize for depth of focus, all the OPC [optical proximity correction] stuff, everything you do for 193, you do for EUV. This means the competency of the lithographers is the same, which is a very becoming feature.

"In terms of what's different though, as you scale down wavelengths, materials that were once transparent become opaque.... By the time you get down to 13 nm, everything is opaque. So the main difference with EUV all relates to the fact that we're operating at 13.5 nm, which means that all materials there are opaque. This means that instead of having transmissive lens elements, everything is reflective, everything is mirrors. Instead of operating in an air ambient or a nitrogen ambient, we have to operate in a vacuum."

Shell explained that in EUV, pellicles (which are transmissive) can no longer be used to protect the masks from contaminants and other damaging factors. "You may have something like a reticle carrier when shipping or storing and even potentially when inspecting (the mask), but when you actually expose the reticle, that cover has to come off. So you have to be really certain that you're operating in a clean environment."

When it comes to defects, Shell said "a lot of what we're going to do is put down programmed defects on the masks and print them and see what happens...figure out which defects we need to worry most about—that's one of the big things we're using the MET for." She added that there has been a significant amount of defect modeling carried out at Lawrence Livermore and Lawrence Berkeley national labs. Plasma, debris mitigation, and other related modeling studies have also been done at the universities of Illinois and Nevada-Reno as well as at Argonne National Lab.

"We've done a lot of modeling...on how printable defects will be and then doing the defect repair. Is there a way to repair if it's embedded in the multilayer (of the mask), if it's on top of the substrate but under the multilayer, and so on. Do we need to do inspections for defects actinically, meaning at wavelength, at 13 nm, or can we do it using optical-type inspection, which is more around 257 nm right now, and scaling down from the inspection suppliers?"

Shell said her group plans to make presentations at the international EUVL symposium in Miyazaki, Japan, in early November as well as at SPIE Microlithography 2005 in San Jose. (For more info on Intel's EUVL program, see the September 2004 issue of Technology@Intel magazine.) —TC