INDUSTRY NEWS

Cypress opens tech center

Cypress Semiconductor's Silicon Valley Technology Center (SVTC) provides the company's 65-nm R&D services to start-ups and established chip firms seeking to develop novel silicon applications. The San Jose–based chipmaker says that partners can use its established fab infrastructure and state-of-the-art equipment in a secure IP environment, with best-practice offerings in fab process engineering, SPC, failure analysis, and design-for-manufacturing methods. "SVTC offers its customers an alternative strategy for taking a product from proof of concept to manufacturing," notes Chris Seams, Cypress's executive vp of technology and worldwide manufacturing.

Matrix Semiconductor has already taken advantage of the new center, where it developed a high-volume approach to making its 3-D nonvolatile memory product before transferring the technology to a foundry. "SVTC has enabled Matrix to build prototypes that have transferred successfully to our foundry quickly and cost-effectively, something we were unable to do in a pure lab environment," explains Siva Sivaram, Matrix's COO. "SVTC experts handled all the wafer manufacturing and equipment maintenance, which allowed us to focus on our product design."

Soitec, ASM push sSOI

Soitec and ASM International say they have made a "major breakthrough" in joint development efforts to enhance strained-silicon-on-insulator (sSOI) substrates. The collaborators claim to have successfully introduced a wafer-level strain, which should extend the technology well beyond the local strain now in use. The companies have developed substrates that feature extremely high-quality, wafer-level strain without the elevated levels of crystal defects that have heretofore plagued the process. Defectivity levels of the strained layer have been reduced between 100 and 1000 times lower than the industry standard, according to the partners, nudging the quality of sSOI close to that of bulk silicon and SOI.

Soitec has been sampling 200-mm sSOI since 2Q2003 and is upgrading its 300-mm sSOI production line in Bernin, France—said to be the first of its kind—for sampling and pilot manufacturing. "The ability to innovate and improve the standards of the strained silicon epitaxial process is expected to lead to a broad portfolio of sSOI products," says Soitec CTO Carlos Mazure. "Our customer and internal evaluations show that the strain of sSOI is very robust, surviving the typical thermal budgets of 65-nm processes."

CD-ROM explores MEMS

An updated version of the World of Microsystems CD-ROM has been issued by Yole Développement and its publishing partners. Divided into three main sections—markets, technologies, and products—along with a general overview, the interactive disc features several tiers of information. The chapters on eight markets—aerospace/ defense, automotive, environment, home appliances, IT/entertainment, medical/biomedical, process control/ instrumentation, and telecommunications—are subdivided into easy-to- navigate areas titled "why," "economics," "markets," and "manufacturers." The other two main sections have similarly intuitive features. The technologies component includes detailed explanations of 27 MEMS manufacturing steps listed under six main categories, while the products section focuses on 10 different commercial goods that employ microsystems. For information on how to purchase the World of Microsystems CD-ROM, contact Sandrine Leroy at leroy@yole.fr.

New ISO documents issued

The International Organization for Standardization (ISO) has released three new cleanroom-related documents, according to the Institute of Environmental Sciences and Technology (IEST). IEST serves as the secretariat for ISO Technical Committee 209, which developed the documents.

ISO/FDIS 14644-5, "Cleanroom and associated controlled environments—Part 5: Operations," offers information for establishing a sound operational cleanroom program and defines essential requirements for maintaining cleanliness during cleanroom operations. ISO/FDIS 14644-7, "Cleanrooms and associated controlled environments—Part 7: Separate devices (clean air hoods, gloveboxes, isolators, and minienvironments)," specifies the minimum requirements for the design, construction, installation, testing, and approval of separate enclosures where they differ from other ISO documents. ISO/FDIS 14644-8, "Cleanrooms and associated controlled environments—Part 8: Classification of airborne molecular contamination," assigns ISO classification levels to specify the limits of AMC concentrations within a cleanroom and associated controlled environments.

Metrology event seeks papers

The 2005 International Conference on Characterization and Metrology for ULSI Technology is looking for papers. The biannual event will take place March 15–18 at the University of Texas campus in the Dallas suburb of Richardson. Conference organizers seek papers on a variety of related topics, including 300-mm metrology, real-time control and monitoring, integrated metrology, ultrashallow junctions, defects, interconnects, silicon-on-insulator materials, lithography bottlenecks, novel measurement methods, and metrology for nanotechnology devices. One-page abstracts should be sent to erik.secula@nist.gov by November 1. For more information about the conference, log onto www.eeel.nist.gov/812/conference.