This issue's Hot Button examines the role played by interconnect-related issues on the road to the 45-nm technology node. We've assembled some intriguing comments made during a recent panel discussion that shed some light on what lies ahead in the areas of low-k materials, copper PVD/ALD and CMP, electroplating, etch, and cleaning.

Applied Materials hosted the panel, titled "The New Reality: Breaking Through to 45 nm," at the International Interconnect Technology Conference held in Burlingame, CA, in early June. Moderator Mark Pinto, senior vice president of Applied's new business and new product group, started the event with an overview of the key challenges facing back-end-of-line (BEOL) integration as the industry moves down the technology curve. Pinto's concluding slide depicted some of the daunting integration obstacles looming in the path to 45-nm yield maximization, such as poor interlayer and copper adhesion, tensile stress, thermal instability, weak cohesion, low modulus and hardness, and poor via etch selectivity.

Here are some excerpted comments from the panelists. They address such issues as the necessity of porosity in lower-k-value films, the challenges of etching new materials, the extension of PVD and eventual transition to ALD, and some intriguing research on planarizing and cleaning fragile low-k structures.

FARHAD MOGHADAM (vice president, dielectric systems and modules, Applied Materials): When you get down to k-values of less than 2.5, there's no magic; you have to have porosity. For bulk material, a certain amount of k-value, down to about 2.7 or 2.8, can be reduced by carbon doping. But if you want to go beyond that, you have to incorporate porosity.

Once it gets to that point, the k becomes tunable, between 2.1 and 2.5, and it has to pass nine layers of integration with your barrier, achieving the right hardness and modulus.... When you deal with porosity, you have to control the pore radius, the distribution of porosity, the percentage of porosity, the connectivity of pores (unconnected versus connected), and then you need to have tight distribution to avoid the killer voids. Remember that you cut the via through these films and you have to deposit barrier seed which has to be a continuous, very thin layer of film, so your pore sizes cannot be very large.

JOHN SUDIJONO (project leader, CHRT-IBM Alliance, Chartered Semiconductor): I think it is clear that for us to etch different kinds of low-k materials, we need to have chambers and a process window that is large enough for us to tune the process, so that the operating window is compatible with all the low-k materials, and that this has to be done with very little or no damage. In order to do that, we're going to have to characterize the energy distributions, the plasma densities, and basically understand each of the processes. Having determined those process conditions, we're going to have to turn those process conditions into process knobs or tuning knobs on the tool itself, be it hardware or a number of things with the chemistry itself, to allow for process customizations within a complex integration scheme. The result of this would be to control the CD uniformity itself within plus or minus 10%.

The other point is that we need to push for a true and complete cleaning capability on the chamber itself. When we are dealing with the successive etch steps for these different materials, these film stacks, we're going to have to remind ourselves that there is a possibility of crosstalk from process 1 to process 2 and so forth. We need to make sure that we eliminate the crosstalk between these processes. The integrated resist strip is obviously desired; if it is not done for in situ capability, it will have to be done on a common platform. [Integrated resist strip] is ultimately desirable because we can improve the fab cycle time.

STEPHEN ROSSNAGEL (research staff, IBM T.J. Watson Research Center): I think we're somewhere between our fourth and fifth copper generation using PVD, and the question is: is something going to change? Usually this comes from senior management who say that obviously it's not going to work for another generation, and all of a sudden, it does. PVD scaling is, for the most part, geometric. In fact, we often look at a percent of the linewidth; we often scale from one generation to another just doing a percent shrink from the last generation, but eventually that fails when the films fail. Typically it stops being a barrier, it stops being a continuous seed layer, and even though the PVD technology keeps getting more sophisticated, there's eventually a problem where the weakest point on the film is just too thin, in terms of conformality.

From what we see from barriers for PVD, the minimum is on the order of a nanometer, one to one and a half. Actually we've worked it out to a half a nanometer for the barrier, but typically [it's] one to one and a half, and the seed thickness is about 3 or 4 nm on the sidewalls, which then leads to these typical field thicknesses that you usually see written down. PVD is comfortable in that environment. But the problem is, as you scale down from 45 nm to 32 nm, where we see it break first is in the copper continuity on sidewalls; typically the middle of the sidewall becomes a void, because the copper is simply no longer continuous. The geometric scaling worked but the film is not quite there.

We've heard a lot about ALD, and we've been working with ALD at IBM since the late 1990s. It turns out that the first ALD transition is in tantalum nitride. This isn't necessarily the most broken film from the PVD point of view, but it was the most straightforward approach. This is an upgrade, if you will, it's a one-to-one swap, which is actually nice from an integration point of view. We'll probably see this back into the 65-nm generation, generally because the tool exists and it can be done.

The downside is that there was no ALD tantalum or copper for the most part. We spent a lot of time on halogen-based tantalum, but halogens are not really desirable in a copper enivronment, and there's no good copper ALD that we've seen yet. One potential switch for this is to migrate from tantalum copper to ruthenium directly. Ruthenium is a directly platable material, it is not a diffusion barrier. It would still need a tantalum nitride barrier. But you can plate on ruthenium, and there are a lot of interesting opportunities there. There are obviously a lot of concerns too. There are tool issues, there's a deposition process for the material, there's a plating process and a polishing process, and there are a number of integration issues relating to how you utilize these films, whether you use them in a sacrificial mode or not. There are electromigration issues that look good so far, as well as other issues relating to stress, porosity, and so on.

But in any case, we're looking ahead and saying PVD is certainly there at 65, could be there at 45, but we don't know for sure. Tantalum nitride ALD is coming in, and ruthenium is an interesting option.

REINHOLD DAUSKARDT (professor, Stanford University): Let me say something about the [cleaning] step. You plunge these incredibly fragile materials into aqueous solutions, which has got to be about the worst possible thing that you can do. Let me [discuss] some of the characteristics of what happens. Here we are interested in the rate at which a defect will grow.... The key here is to make sure that any defects evolve as slowly as possible. [In terms of ]the rate at which a crack will grow in the dielectric as a function of the mechanical driv- ing energy, the highest value would be the critical fracture energy.... One curve is measured in a pH of 3, in an acidic environment, the other one is measured in a pH of 11. In an aqueous solution, as you increase the pH from acidic to basic environments, the rate of evolution of any defects or cracks in the dielectric materials is going to go up dramatically. This is a well-established phenomenon: as you increase the hydroxyl ion concentration, the growth rates go up.

What we believe is really critical for yield, for device reliability (particularly through CMP and also through post-CMP cleaning processes) is the thresholds for crack growth. This is where devices live. No device can tolerate being on this curve, because clearly within seconds the defect will have evolved to tens of nanometers, maybe even microns. So the key is to live below these thresholds.

There are a number of ways you can do that. You pick materials that have the highest possible thresholds, or you design materials that have high thresholds. The other thing you can do is to make sure you don't put [the materials] in a highly basic environment. CMP solutions are nearly always formulated to be extremely basic. The other thing you can do is to lower the residual stresses . . . in the device structure. Here's an example of what can happen when you change the chemistry of the solution. Something that's very commonly done in CMP slurries is to use hydrogen peroxide. Look what it [does] to the crack-growth threshold. You might have been safe operating in a pH 11 solution, which is a slightly acidic solution, but the hydrogen peroxide greatly accelerates the crack-growth-rate behavior, and it moves this threshold to much lower values. Your device basically would not survive this.

In the past couple of months, we've actually been looking at some commercial post-CMP cleaning solutions, and to our absolute shock, we are finding that the crack-growth-rate curves are way above the pH 11 curve. It is absolutely remarkable that after taking this incredibly fragile device and shepherding it through all these processes, your final clean is to put in a solution that is going to accelerate defects and crack growth even further.... You can't simply make structures with these materials without paying really close attention to how they're processed subsequently.