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Introducing wide-band-gap silicon carbide production into a silicon fab

Joseph Shovlin, Richard Woodin, and Tony Witt, Fairchild Semiconductor

Silicon carbide (SiC) is an attractive alternative to silicon for certain applications. SiC’s wide band gap, high thermal conductivity, and high electron mobility provide the needed material properties to fabricate high-voltage, high-power devices.^1–3 The ability to produce high-performance circuits using SiC without significant new investment in cutting-edge fabrication tools is particularly appealing.

Table I compares several wide-band-gap materials to silicon.⁴ Gallium nitride (GaN) has good mobilities but is hampered by low thermal conductivity and the limited availability of GaN substrates. While diamond has the highest mobilities, large-area single-crystal diamond substrates are not available, and diamond has no n-type dopant. SiC, however, has the large band gap and high thermal conductivity necessary for elevated-temperature operation, mobilities that enable high-speed switching, and low dynamic power loss. For example, SiC compares favorably with silicon in diodes: switching speeds above 100 kHz are attainable with dynamic power losses 5–10 times better than silicon.

Table I: Selected properties of silicon and several wide-band-gap materials.

The Advanced Materials Group of Fairchild Semiconductor has been tasked with bringing SiC device production into an existing silicon fab in South Portland, ME. The goal is to develop processes that maximize the utilization of the existing fab infrastructure. This article discusses some of the challenges that the group has faced and how it has addressed them. Although the processes used to fabricate SiC devices are similar to those employed to make silicon devices, there are several important differences.

Cost of Material

Figure 1: An optical micrograph of four micropipes in SiC. The dark spot is the opening of the micropipe; the tube can be seen penetrating the semitransparent wafers.

High-quality, large-surface-area, and low-cost silicon substrates are readily available. In order to improve profit margins, much effort is expended to achieve small decreases in manufacturing costs and small increases in process yields. SiC substrates, however, are only commercially available in up to 3-in.-diam wafers, with relatively high defect densities. The net yield reduction opportunity on the best wafers caused by material defects can be as high as 40%, depending on device size. Defects in SiC substrates include visual defects and micropipes (see Figure 1), which are open core-screw dislocations that propagate through the boule and leave micron-sized holes, which then penetrate the substrate.⁵ Visual defects include chips and scratches, areas of undesired polytypes, and other substrate anomalies.^6,7

If epitaxy is employed on small volumes of wafers, the best wafers can cost more than $5000 per slice. Because processing costs per wafer are fixed—and much lower than the substrate cost—the purchase of lower-cost, lower-quality wafers, with yield reductions of up to 53%, can actually decrease per-die cost (see Table II). Yield reduction caused by micropipes depends on the die size; in Table II, a die size of 1 mm2 is assumed. High material cost allows slower, more manual processes to have less effect on a die’s sale price. For silicon production, fabrication cost would dominate; however, for SiC it is only 10–20% of the total cost of a finished passivated wafer.

Table II: Recent prices for 2-in. SiC wafers (without epitaxy).

Because of the high cost of substrate material, the processes discussed in this article use 1-cm² wafers diced from 2-in.-diam wafers. A 2-in. wafer can be diced into 16 usable 1 x 1 cm square wafers, which are referred to as “coupons,” with a few small corner/wedge pieces left over. Processing conditions and device design parameters can be varied so that 16 experimental “splits” can be obtained for the cost of one wafer. After developing the process on coupons, it is transferred to whole 2-in. wafers for production.

Material costs will decrease over the next few years as the market for SiC devices expands. The SiC wafer market is dominated by a single supplier. However, several competitors are expected to bring product to the market within the next year. Wafer sizes and quality are steadily increasing, which also drives down the cost per unit of usable area.⁸

Processing Considerations

Many of the processes used in SiC device manufacturing are identical to those employed in silicon device production, including wafer cleaning, photolithography, metal and oxide thin-film deposition, and etching. However, two common silicon production processes are quite different. The dopants implanted in SiC do not readily diffuse, and there is no practical SiC wet etchant.^9,10 While the metal deposition method doesn’t differ between the two processes, the metal films commonly used in SiC diverge from those used in silicon-based devices.

Doping. Doping considerations complicate SiC device design. The doped regions in SiC can be created either by doping during epitaxial growth (and etching back to form device structures) or by ion implantation. The epitaxial growth of doped SiC layers is performed with hot- or cold-wall CVD, using such typical precursors as SiH₄ and C₃H₈.¹¹ Temperatures typically exceed 1500°C. Epitaxial doping is accomplished with site-competition epitaxy. By lowering or raising the silicon-to-carbon ratio in the presence of dopants, a doped film is grown. Aluminum is typically substituted for silicon for p-type epitaxy, and nitrogen is substituted for carbon for n-type epitaxy. Commercial epitaxy costs add up to about $1000 per wafer per layer.

Dopants do not readily diffuse in SiC below 2000°C, which presents a problem since SiC sublimes above 1600°C. Since ion implantation at 400 keV only penetrates to a depth of approximately 0.5 µm, doping must be used during epitaxy for thick layers, such as drift regions. Boron and aluminum are typical p-type implants, while nitrogen is the common n-type implant.

A further complication in the fabrication sequence is that implanted impurities have to be activated by annealing between 1000° and 1700°C. Furnaces capable of these temperatures are not found in the typical silicon fab. Generally, these high-temperature anneals are performed in vacuum furnaces, either with refractory-metal resistively heated elements or through RF-induction heating. For temperatures above 1600°C, the surfaces of the production wafers must be protected by sandwiching them with SiC dummy wafers or by maintaining a silane overpressure during the anneal.

Etching. SiC etching presents further problems. Molten potassium hydroxide is not practical for SiC wet etching. The dry-etch contrast ratio between SiC and typical mask materials is low. Deep etching requires a hard mask, typically aluminum or nickel, and the presence of a fast-diffusing metal such as nickel within the silicon CMOS fab requires special contamination control precautions.

Metallization. Most as-deposited metals form Schottky contacts to SiC, while ohmic contacts develop from as-deposited Schottky contacts by annealing at elevated temperatures. Nickel is typically used as the ohmic contact to n-type SiC; in order to make it ohmic, it must be annealed at 600°–1000°C. To protect device performance, the deposition and annealing of nickel as a back metal for n-type SiC wafers is generally performed early in the process flow. The presence of a back metal causes tool contamination concerns in subsequent processing steps. SiC material is usually processed on machines about to go into preventive maintenance cycles. Silicon test wafers are run before and after SiC to ensure the safety of the process to be built. As an added safeguard, some front-end tools are off limits to SiC processing.

Tooling Considerations

When 2-in.-diam substrates are made in a 4-, 6, or 8-in. silicon fab, they are basically equivalent to 1-cm² coupons: special carriers are needed to trick tools into “thinking” that they are processing full-sized wafers. The same techniques used to process coupons are necessary to process 2-in. wafers. For tools with vertical feeds, limited feed sizes, or weight restrictions, carrier development can require creative solutions. Carriers must securely hold the coupons, survive adverse processing conditions, be inert to silicon process contamination, and stay relatively economical in terms of cleanability and price. The following subsections address tooling issues raised in the SiC photolithography and thin-film processes.

Photolithography. There are two primary sources of challenges to SiC photolithography in a silicon fab. Both SiC wafer size and quality deviate substantially from the silicon norm. In order to be processed in modern lithography tools, small-diameter SiC wafers require creative fixturing or substantial equipment modification. The use of small coupons to enable economical developmental studies further exacerbates the dilemma of poor wafer quality. Because of materials properties and market conditions, the wafer dimensional quality of SiC lags well behind that of silicon. The specifications for wafer bow and total thickness variation (TTV) for SiC wafers being supplied are not explicit. Typically, numbers in the range of <40 µm for bow and TTV are cited, but often supplier specifications do not include any specific, written amounts. While most wafers appear to meet or exceed this unwritten spec, there is no assurance that a specific wafer will not deviate significantly from flat and parallel. As wafer purchase volume increases and more vendors enter the market, it will be possible to demand tighter control of bow and TTV and incorporate those improved values into an acceptance specification.

The approach used to pattern 1-cm² SiC coupons is an example of transferring a process into a preexisting facility. The fab’s primary process involved the exposure and patterning of 2-in.-diam, 3-mm-thick silicon wafers. The available mask aligner was a 2-in. contact tool specifically set up to handle the thick wafers. Photoresist spinning was done manually on a programmable spinner, and an oven and hot plates were available for baking. Resist development was performed in a batch bath process.

Spinning resist onto the very small coupons required hand loading of the spinner. A small (about 8-mm-diam), flat vacuum chuck was sufficient to hold the piece during spinning. Each coupon was laid on the chuck and coated with resist from an eyedropper, after which the spin cycle was started. Soft baking was accomplished by gravity contact on a hot plate. The resulting resist films near the center of the coupons were adequate for patterning, but the coupon corners and large edge-to-area ratio inherently resulted in a photoresist bead over a significant fraction of the sample. In a normal silicon operation, nearly the entire 1-cm² coupon would probably be considered edge. This definitional conundrum leads to questions about the estimation of yields from small “wafers” since the areas beneath substantial resist beads cannot expose and pattern properly. Occasionally, the beads near corners were thick enough to prevent a gap during the alignment process; in such cases, the resist was stripped and the coupon reworked.

The alignment and exposure of the small coupons required the use of a secondary vacuum chuck (shown in Figure 2). Most contact aligners go through a planarization process prior to alignment and exposure. On the aligner used in the work reported here, a stamp contacted the wafer at three points to establish the position and orientation of the wafer surface. For this aligner, these three points were near the edge of a 2-in. wafer, only one of which could possibly coexist with a 1-cm coupon. To address this issue, four shims from the coupon wafer were mounted onto the vacuum chuck along with the coupon to be exposed. These shims were typically the odd-shaped remnants left over after a 2-in. wafer was diced on a 1-cm pitch, with the 1-cm (or nearly 1 cm) pieces retained as test specimens.

Figure 2: The front and back of the secondary chuck, which features three shims for planarization, a center shim for contact sensing, and a 1-cm2 coupon over the five-hole pattern. Channels from the front to the backside transfer vacuum.

The sample was positioned at the five-hole pattern offset to the left of center. This offset allowed the coupon to sit beneath one objective of the split-field microscope. The shims were placed over the three holes around the perimeter of the chuck as well as over the center hole. The perimeter holes coincided with the stamp contact points. The wafer center was used by the system to determine that stamp contact had been made through the use of a nitrogen back pressure at the central nozzle. The backside of the secondary chuck was milled with pockets around the through-holes, in order to channel the vacuum. With the coupon and four shims held in place by vacuum, the planarization algorithm could bring the coupon surface approximately parallel with the mask plane at a controlled spacing. Once planarized, the mask could be mounted as usual and the sample aligned and exposed.

The use of this lithography system for such small wafers was laborious. All sample and shim placement had to be done manually. The risk of the small coupons and shims falling into the aligner mechanism was substantial; occasionally, the system had to be dismantled to allow recovery of pieces lost because of poor vacuum hold or transfer-arm malfunction. The small coupon size also complicated the alignment to the mask. The alignment marks were too close together to permit the use of the split-field image. Marks on opposite sides of the coupon had to be iteratively viewed and adjusted to reach final alignment, leading to a protracted alignment period.

Wafer bow and TTV could also significantly affect the process. If the wafers were perfectly flat and parallel, the shim system would lead to an ideal planarization; but any wedge or bow means that the surface created by the three-point shim contact is not necessarily coincidental with the coupon surface. Generally though, these less-than-ideal contact-printing conditions could be overcome with careful use of the procedure detailed above. The use of a stepper (with its small depth of focus) on these small coupons is under evaluation. The introduction of 2- or 3-in. wafers into an existing 6- or 8-in. lithography line will probably encounter many of the same challenges seen during the patterning of 1-cm² coupons on 2-in. tooling.

Thin-Film Deposition. In a 4-, 6-, or 8-in. silicon fab, most tools run automatically with cassette-to-cassette operation. Carriers must be developed that can function in a cassette-to-cassette mode and meet multiple requirements. First, they have to securely hold the coupons or 2-in. wafers. It is not acceptable to shut down a manufacturing tool to take it apart and recover a slipped wafer. Second, the carriers must fit in the cassettes and be narrow enough to enter the tool. Third, they must withstand the tool process environment. Fourth, the carriers cannot contaminate the tool. So even in a fully horizontal, cassette-to-cassette operation, complications may develop.

A 6-in. dielectric deposition tool was used at the fab. Initially, holder design did not seem to be very challenging. The system was fully horizontal, wafers were not exposed to high-flow gases that might blow small pieces off a carrier, and internal temperatures were moderate (about 400°C). The tool ran 6-in. wafers cassette to cassette, with robot-arm transfer between the entrance chamber and the processing chambers.

Figure 3: Six-inch machined aluminum carrier; although disposable and easy to machine and clean, it warped under film stress.

Figure 4: Six-inch machined stainless-steel carrier with milled pockets; while it held up to processing stresses and was cleanable, it proved prone to etch damage.

Because the tool was designed to run 6-in. silicon, this was the starting point for carrier design. The first carrier tested was a thick 6-in. silicon wafer milled with six 1-cm² pockets. While the carrier functioned properly, it was quickly abandoned since it was difficult to machine the silicon carriers, was hard to clean after machining, and was very fragile. The pockets held the coupons well enough that the concept was not abandoned. The second carrier was aluminum (see Figure 3). It was easier to machine and clean than the first prototype and was inexpensive enough to be considered “disposable.” But it warped under stresses induced by oxide film growth. The third carrier (shown in Figure 4) was stainless steel. Initially, it was too heavy to be carried by the robot arm within the tool. After milling pockets in the surface to lighten the carrier, it met the physical requirements necessary for the process. The carrier pictured in the figure can hold as many as six coupons at a time.

Figure 5: Six-inch machined titanium wafer carrier, which is lighter than stainless steel, withstands processing stresses, features excellent cleanability, and can hold four 2-in. wafers.

Since the stainless steel etched slightly in buffered-oxide etch (BOE), it required bead-blasting to clean off the oxide coating. For manufacturing purposes, an inexpensive, disposable, etchable holder is preferred. For this reason, the 2-in. wafer holders were made of titanium (shown in Figure 5), which is not only inert to BOE cleaning, but is lighter than the stainless-steel model. Slots have been machined that allow 2-in. wafers to be picked up with wafer tweezers or vacuum wands. After the carrier was built, it was necessary to ascertain whether silicon production was being affected by any contamination of the growth chamber. Silicon test wafers were run before and after SiC processing, and no deleterious impact was seen on the silicon process.

Conclusion

The state of wide-band-gap semiconductor technology matches that of silicon technology in the late 1970s. Wafers are typically ≤4 in., highly defective and costly, and process techniques are in the development stage. But unlike the early days of silicon device processing, wide-band-gap technology developers can learn from more than 30 years of materials processing development and fabrication improvements. As a result, new materials can be developed and integrated into commercial products more rapidly than in the past. With the enthusiastic help of the technical staff members of the modern silicon fab, including both process and tool maintenance engineers, wide-band-gap production and development can be successfully piggybacked onto the operations of a modern silicon fab.

Acknowledgments

This article is a revised version of a paper presented at the IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC) in Boston, May 4–6, 2004. The members of the Advanced Materials Group would like to acknowledge the efforts put forth by the support and engineering groups at Fairchild Semiconductor’s South Portland, ME, fab. Their flexibility, expertise, and hard work are greatly appreciated.

References

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Joseph Shovlin, PhD, is a staff engineer in the Advanced Materials Group at Fairchild Semiconductor, South Portland, ME. Before joining the company, he was a member of the silicon carbide development group at Extreme Devices in Austin, TX. He has worked on silicon carbide development for more than five years. Shovlin received a PhD in physics from Ohio University in Athens. His doctoral research was in the characterization of the electrical emission properties of natural and artificial diamond and other wide-band-gap semiconductors. (Shovlin can be reached at 207/775-8352 or joseph.shovlin@fairchildsemi.com.)

Richard Woodin, PhD, is a senior member of the technical staff and the leader of Fairchild’s Advanced Materials Group. Before joining the company, he managed the silicon carbide development group at Extreme Devices. Woodin was the president and chief technical officer of Crystalline Materials and Crystalline Manufacturing, where he managed the technical scale-up and commercial sales of synthetic diamond products. From 1979 to 1989 he was a chemist at Exxon Research and Engineering, ultimately becoming a senior staff chemist there. Woodin received his PhD in chemistry from the California Institute of Technology in Pasadena. (Woodin can be reached at richard.woodin@fairchildsemi.com.)

Tony Witt, PhD, is a principal process engineer in Fairchild’s Advanced Materials Group. He has spent the last three years working on process development of silicon carbide electronic devices, beginning at Extreme Devices. Witt was involved for nearly 10 years in materials research related to space-based nuclear energy conversion, including in-core electrical insulator development and bulk metals CVD. He became involved with semiconductors as a staff scientist at Iowa State University in Ames, with projects involving amorphous silicon on flexible substrates as well as various other materials topics. He received a PhD in materials science with an emphasis on electronic ceramics from Northwestern University in Evanston, IL. (Witt can be reached at tony.witt@fairchildsemi.com)