In March’s Hot Button, we asked several industry experts what they thought were some of the critical issues in the broad field of metrology, inspection, and review in semiconductor manufacturing. Their answers mostly focused on patterned-wafer and general yield challenges, such as high-aspect-ratio inspection, nonvisual defects, hidden profile errors, systematic yield loss, and other anomalies that keep fab engineers and their bosses up at night.

In this installment of The Hot Button, we solicited the opinions of another group of measurement-minded authorities about what they see as the critical metrology demands for starting materials, in particular bare wafers and engineered substrates such as silicon on insulator (SOI). Although polished and epitaxial wafers will be used into the foreseeable future, SOI, strained SOI, and the like are here to stay. Some prognosticators believe these bonded, highly engineered wafers could eventually dominate the starting materials world.

Our participants’ comments begin with concerns about how silicon houses can afford simultaneous 200- and 300-mm advanced development while being pressured to reduce wafer costs by their customers. The SOI arena gets attention next, with many of the differences between bulk-silicon and engineered-substrate metrology discussed and dissected. We conclude with a 30,000-foot view from Alain Diebold, International Sematech’s senior fellow and master of things metrological.

William Hughes (associate fellow, metrology, MEMC Electronic Materials): As the introduction of 300-mm wafers continues at an accelerating pace, it is easy to forget that the real workhorse of today’s semiconductor industry is the 200-mm wafer. The technical and economic climate is different from what it has been in the past; many 200-mm-product device lines are being reinvented to mirror the smaller design rules associated with 300-mm products. The conservation of capital dollars and human resources requires that the industry extract more value from existing facilities.

This new metrology must pay for itself through improved cost of ownership in order to justify replacing existing systems. —William Hughes

This dilemma is even more pronounced within the silicon-wafer supply chain. Silicon-wafer metrology and production processes achieved maturity with a set of product specifications that barely resemble these new requirements. Instead of being afforded the luxury to produce 200-mm wafers with the installed toolsets, silicon manufacturers are under pressure to develop new processes, new back-surface conditions, and new measurement capabilities to extend 200-mm product applications beyond the original expectations. The historic culture in our industry provides another constant to this situation: these better wafers must be less costly.

A resolution to this situation requires a complementary push from metrology suppliers to introduce new 200-mm tools or 300-mm clones with the accuracy and precision of the 300-mm counterpart tool. Moreover, this new metrology must pay for itself through improved cost of ownership in order to justify replacing existing systems in these mature lines. Without the resultant improved cost of ownership in 200-mm metrology, it will be difficult to advance this mature product into an even-higher-quality middle age and challenge 300-mm dominance.

Mike Kirk (vice president and general manager, Surfscan Division, KLA-Tencor): For the past few years, silicon-on-insulator (SOI) has been in production for a select number of high-end microprocessor applications. As the recent string of announcements from Sony, Freescale Semiconductor (formerly Motorola SPS), and Chartered shows, SOI is seeing increased adoption at the 90-nm node. However, it is not likely that SOI and other engineered substrates, such as strained silicon and strained silicon on insulator (sSOI), will move into mainstream production until the 65- and 45-nm nodes.

Process control is essential to cost-effective wafer substrate production. Surface defectivity, uniformity, and nanotopography, which are major quality metrics for bulk wafers (polished silicon and epitaxial), continue to play an important role with respect to engineered substrates. Achieving a defect-free wafer, however, has taken on much greater importance for engineered-substrate qualification. Some of the defects found in SOI processing are common to bulk substrates, such as scratches and particles. However, SOI also introduces new and unique defect types, such as surface voids, which are highly yield critical.

Defect-detection requirements for engineered substrates are, for the most part, identical to those for epi wafers, meaning that defects that are sized at the design rule (e.g., >90-nm size at the 90-nm node; >65-nm size at the 65-nm node) must be detected. However, engineered substrates pose inspection problems not previously encountered with bulk substrates, which has proven to be a major challenge for wafer manufacturers.

One of the greatest chanlleges with SOI wafer inspection is the fact that the substrate is multilayered."—Mike Kirk

One of the greatest challenges with SOI wafer inspection arises from the fact that the substrate is multilayered. Visible-wavelength illumination, which is used in traditional surface-inspection systems, penetrates the top silicon layer and buried-oxide layer of the SOI substrate. Reflections from these interfaces interfere constructively or destructively at the tool’s collectors, depending on the thicknesses of the individual SOI layers. These interference effects cause false and inconsistent defect readings and reduce overall inspection sensitivity.

Another important difference between bulk and engineered substrates that affects inspection is that many more process steps are required to manufacture engineered substrates than are needed for traditional polished and epi wafers. As a result, three to four times as many inspections are required to ensure defect-free substrates. The result of this is a significant rise in the inspection cost of ownership unless a corresponding increase in inspection throughput can also be achieved.

For years, traditional wafer-surface inspection has proven capable of meeting the sensitivity requirements for traditional polished and epi wafers. With the increased adoption of SOI and other engineered substrates as well as the need for greater levels of sensitivity at the 65-nm node and beyond, it quickly becomes evident that new surface-inspection techniques are needed to meet future production requirements.

Christophe Maleville (process engineering manager, Soitec): As device design rules shrink, the most recent International Technology Roadmap for Semiconductors (ITRS) calls for reductions in threshold and defect density. These requirements are driving the introduction of a new generation of light-scattering metrology tools. Here’s why: In terms of metrology, the optical response of an SOI wafer is affected by its structure. Under the current generation of tools, it is the wafer itself, rather than the tool settings, that drives sensitivity.

A bulk wafer absorbs transmitted light. With an SOI substrate, however, part of the transmitted light is reflected at the buried interface between the top silicon film and the layer of insulation below it. Incoming and reflected beams interfere with each other, which changes the SOI substrate’s apparent reflectivity. Defect detection is therefore affected by the silicon and buried-oxide thicknesses. Whether the scattering is increased or decreased depends on whether the interference is constructive or destructive. This, in turn, affects whether defects appear oversized or undersized. The current toolset can compensate for this by employing a dedicated calibration curve for each thickness combination, which adds complexity to the manufacturing scenario.

At the 90-nm node, enhanced inspection capabilities are required. The upcoming tool generation has already demonstrated a 60-nm defect-detection threshold for SOI wafers with polystyrene latex spheres deposited on them, which will satisfy industry needs down to the 45-nm node. Reflectivity dependence of detection is eliminated, and multiple calibration curves are no longer needed. Scattering simulations are even showing that scattering intensity can be increased as film thickness is reduced below 200 Å. In terms of defectivity, KLA-Tencor’s new inspection system, which is compatible with sSOI generations, still has to be complemented by a nondestructive production system for strain and composition monitoring.

Alain Diebold (senior fellow, International Sematech): A wide variety of starting substrates are used in IC manufacturing. Traditional substrates such as polished and epi wafers continue to be used in manufacturing, even as SOI has become much more than a niche technology. The thickness of the silicon layer is quickly shrinking. Another technology, strained silicon on silicon germanium epi, is also used. Strained SOI and germanium on insulator (GeOI) are being evaluated for future applications.

As new substrates are introduced, the impact of transistor properties must be evaluated.—Alain Diebold

All of these substrates continue to provide many challenges for metrology. Particle and crystal-originated pit (COP) detection continue to challenge metrology. Although detection of ever-smaller particles remains a key challenge, measurement technology often lags behind the needs described in the ITRS. (For example, see “Starting Materials” in the “Front End Processes” portion of the 2003 edition of the ITRS.)

Particle detection on SOI substrates is more difficult than on polished bulk silicon wafers because of the extra optical reflections from the interfaces of the buried-oxide layer. The variation in the thickness of ultrathin SOI and sSOI wafers makes this situation worse. Light scattering continues to be used for particle and COP detection. Over the past several years, suppliers have been steadily improving light-scattering technology through the use of detectors that monitor the specular reflection and detectors that collect light scattered into specific angular regions. Despite all these improvements, observation of the smallest particles requires use of the smoothest possible wafer surfaces. Measurement of thin films on top of SOI and similar substrates is also more difficult. Both ellipsometry and x-ray reflectivity are being improved to meet measurement needs.

Although stress measurement and crystal defect detection are well known, their application to thin SOI and sSOI requires further development. A number of methods are being used for stress measurement. The one that seems to be receiving the most attention is micro-Raman. X-ray diffraction rocking curves also measure stress, and x-ray topographs provide images of crystal defects.

Although it is considered to be difficult to obtain x-ray topographs from very thin films, researchers continue to expand this capability. Some work at the National Institute of Standards and Technology will explore the use of synchrotron-based x-ray methods for future substrates. Photoluminescence is an important method of mapping crystal quality for thin SOI and sSOI.

The measurement of transistor characteristics such as the saturation drive current, threshold voltage, and carrier mobility is critical for each new technology generation. As new substrates are introduced, the impact of these new materials on transistor properties must be evaluated. In addition, carrier mobility measurement must be done at ever-higher frequencies on new substrates.

In short, the use of ultrathin SOI and other engineered substrates has added another layer of complexity to the many challenges facing metrology.