INDUSTRY NEWS

More 300 mm to ramp

Several semiconductor manufacturers are at various stages of expanding their 300-mm-based capacity. Chinese foundry SMIC started receiving the initial production equipment for its Fab 4 in Beijing in early June. Scheduled to begin production in the second half of 2004, the facility is the first 300-mm plant in China. The company says that the fab’s planned capacity is 45,000 200-mm-equivalent wafers per month, an amount it expects to reach by the end of 2005. Infineon and Elpida are among SMIC’s foundry customers.

Elpida also plans to augment its own production, saying it plans to increase production at its Hiroshima fab and build another, larger fab next to it. The up-and-coming Japanese memory chip supplier will raise production capacity at the existing plant from 22,000 to 28,000 wafers per month during the latter half of 2004. Construction has already started on the second fab, which will be almost double the size of the neighboring facility. Maximum capacity of the new plant will eventually reach 60,000 wafers per month, with initial mass production scheduled for the second part of 2005. The total price tag for the new expansion and construction will be more than $4.5 billion, according to Elpida.
Intel will spend another $2 billion on a 300-mm sister fab to its recently
completed Fab 24 site in Leixlip, Ireland. The company says the new module, Fab 24-2, will add 60,000 sq ft of manufacturing cleanroom space. Production of 65-nm technology is scheduled to start by the first half of 2006. An agreement with the Irish Development Authority, which includes various grants and incentives, helped pave the way for the additional investments. Intel has spent approximately $6 billion on its Irish operations since 1989.

Nantero, LSI go nano

Nanotechnology developer Nantero and chipmaker LSI Logic have teamed up to develop semiconductor process technology that employs carbon nanotubes in CMOS fabrication. The joint development project is under way at LSI’s Gresham, OR, campus. The companies say that the high electrical and thermal conductivity and tensile strength of carbon nanotubes make them attractive for electronic device applications, properties that enable possible performance breakthroughs through incorporation into existing chips as well as in the development of future semiconductor products. Nantero’s proprietary processes, which are CMOS-compatible, include those focused on the development of a high-density, nonvolatile random-access storage device, or NRAM.

Alliance rosters grow

Three semiconductor industry alliances have bolstered their membership rolls. Taiwan Semiconductor Manufacturing Corp. (TSMC) has joined the X Initiative, the design consortium that supports efforts to develop diagonal interconnect layers. The foundry giant says it has verified the 130-nm X Architecture design rules with test chips and is working to leverage the architecture’s performance, cost, and power advantages. “We’re engaging with select customers on their circuits that employ this new design implementation approach,” explains Genda Hu, TSMC’s vp of marketing. The initiative expects the first production chips using the diagonal interconnects later this year.

The SiLKNet Alliance has added Brewer Science, supplementing the existing focus areas of the low-k materials integration collaboration with a lithography patterning module. The company says it will explore the integration of its bottom antireflective coatings and planarization technologies with leading-edge copper interconnect processes. The addition of Brewer brings the alliance’s total membership to 26 partner companies.

Also on the copper interconnect front, FSI has hooked up with Novellus’s Damascus Alliance. The surface-preparation tool company will install a 300-mm Zeta spray cleaning system in the Novellus Customer Integration Center in San Jose. By placing the system in the center, FSI chairman and CEO Don Mitchell says the company “can more quickly and effectively optimize advanced cleaning processes as part of a fully integrated copper dual-damascene flow.” The tool will be used for postvia and post-trench etches, postbarrier etch cleans, and other copper and low-k surface-conditioning applications.

STMicro, Si Auto sign

Si Automation has signed a three-year contract with STMicroelectronics to provide the chipmaker’s Crolles, France, 200-mm facility with a fabwide fault detection, classification, and data management system. STMicro says it will use the software suite and methodology for advanced equipment control to monitor tool health, reduce process and tool variabilities, and correlate process data to yields. “Data collection is the cornerstone of a successful and efficient equipment engineering activity in the fab,” notes STMicroelectronics’ process control area manager, Stephan Hubac. “The quality of the data collected, its availability, and the information it contains are essential to the success of any equipment engineering activity, which itself is fundamental to the viability of fab operations.”

Sematech, Zeiss team

International Sematech and Carl Zeiss will team up to develop a next-generation aerial image-measurement system (AIMS) for defect review of 193-nm photomasks used in immersion lithography. The German equipment supplier’s semiconductor metrology systems division says that it will produce the first alpha tool in time for release to Sematech and its member companies by 4Q2005. The 193i AIMS technology will be commercially available as early as 2006, which dovetails with the expected introduction of 193-nm immersion lithography into volume production the following year. “The timely development of production-worthy photomask verification and inspection systems will be a critical factor in getting this promising new technology up and running quickly,” says Sematech’s director of lithography, Giang Dao.

MEMS etch control advances

Surface Technology Systems and Jobin Yvon say they have successfully completed first-phase testing on a production-worthy, in situ process control approach for deep-silicon-etch applications in MEMS manufacturing. The collaboration, which has combined Yvon’s ellipsometric sensor technology with STS’s advanced silicon etch system, has resulted in control of the etching process down to 500 µm, said to be some 10 times deeper than the capabilities of conventional methods. Potential applications of the approach include 3-D interconnects, pressure sensors, and inkjet heads. “With this solution, the depth to which we can confidently work is significantly increased, with no intrinsic limitations,” explains Andrew Chambers, STS’s technology director.

Integrated Materials scores

Silicon wafer tower manufacturer Integrated Materials has scored additional funds. The San Jose–based company says it has raised another $8.5 million in a Series B round, which it will use to ramp manufacturing and expand sales efforts. Integrated Materials produces and markets towers that hold wafers during high-temperature deposition and diffusion processes. The company believes its products can replace the existing silicon carbide and quartz material sets. It says its 100%-silicon furnace internals deliver lower cost of ownership, reduced defects, and better yields than the available technologies, as well as eliminating the need to use the acids required to clean the SiC and quartz components. Integrated Materials will offer complete furnace hot zones, including tube liners and gas injectors, by late 2004.