Dry Surface Technologies

Using a tungsten plasma clean process to reduce metal shorts caused by CMP microscratches

Heinrich Ollendorf, Stacey Cabral, and Robert Fuller, Infineon Technologies

A common problem associated with the chemical-mechanical planarization (CMP) processes used in damascene sequences is the generation of microscratches. Microscratches form small trenches in the oxide, which are filled with tungsten during CMP processing. These metal-filled trenches, in turn, can short the intended patterned circuitry.

In tests performed at Infineon Technologies’ wafer fab in Richmond, VA, engineers determined that by introducing a dry plasma clean after the tungsten CMP process, the yield impact of microscratches can be reduced or eliminated. They discovered that the plasma etch process removes tungsten uniformly both from the intended metal pattern and the unintended metal residue in the trench caused by the scratch. The metal short can be eliminated by adjusting the etch depth to the actual scratch depth.

Evaluating Slurry Quality

When the fab migrated from 170-nm technology and ramped at the 140-nm node, engineers observed that CMP-induced microscratches, an example of which is illustrated in the scanning electron microscope (SEM) image in Figure 1, can become a systematic yield detractor and early-life test issue. Further investigations in a high-volume, stable-yield environment revealed that there were variations in CMP slurry quality: different batches resulted in different yields.

Intially, the investigators attempted to develop an in-line method for detecting quality variations among different batches of slurry early on. Defect inspection after tungsten CMP was optimized to detect microscratches.¹ While those inspections were able to detect microscratches, the investigators were unable to correlate the level of scratches to their yield impact. Apparently, the detection signal was not sensitive enough to differentiate between the scratches filled with metal residues that caused yield loss and those in the oxide without metal residues that did not cause yield loss.

The investigators then attempted to perform in-line monitoring of the number of shorts in the test structures of the first metal layer. Since that monitoring step was conducted immediately following the CMP process, the investigators thought that it would provide rapid feedback about slurry quality. This test was more successful than the first one, since the yield loss of the worst-known slurry batch could be correlated to an increase in metal shorts in the test structure. However, it was not possible to establish a yield-loss correlation between metal shorts and batches that were not as bad as the worst-known batch. Hence, a clear correlation between test-structure shorts and product yields could not be obtained. One explanation for this weak correlation is that the test-structure area was not large enough to show a statistically significant impact of the amount of microscratches, since no obvious increase in metal shorts could be observed from one batch to another, with the exception of the worst-case batch.

Figure 1: Tungsten CMP microscratch detected after first-metal-layer patterning.

For these reasons, an in-line evaluation of the effect of slurry quality on yield-relevant microscratches was not possible.

The problem of varying slurry quality was addressed temporarily by creating small test batches (three days worth of production material) from each batch of slurry and, based on yield results, either quarantining the entire batch or releasing it for production. However, this procedure was not feasible over the long term. Process improvements were needed to eliminate the microscratches that were generating shorts.

Two different attempts were made to improve the CMP process itself. First, final table oxide touch-up was extended and optimized to remove a portion of the oxide top layer that was affected by microscratches, and, second, a different slurry and polishing pad were evaluated. However, because these approaches proved to be unsuccessful, they will not be discussed here.

Research Methods

Since it was found that the scratches could not be accurately detected in-line and that they could not be prevented during the polishing process, development efforts focused on the removal of the metal residues inside the scratches. To achieve that goal, a wet-etch application was considered, but it was not pursued for two reasons:

• Trenches filled with tungsten via chemical vapor deposition during the damascene process form a seam in the middle of the tungsten line. Within that seam, contaminants from a wet etch process can become trapped. Even worse, the chemicals can reach the bottom of the contact (since it is applied in a dual-damascene sequence) and affect the integrity of the contact interface.
• If the seam widens, subsequent processes can be affected. For example a titanium nitride (TiN) liner deposited via physical vapor deposition on a tungsten contact layer can become disrupted, since it cannot fill the widened seam at the bottom of the contact. That problem, in turn, can severely affect the fill performance of the tungsten deposition process used to lay down the contact layer.

Therefore, to remove metal residues from the microscratches, the investigators decided to use a nonisotropic plasma etch process.

Figure 2: Cross section of tungsten CMP–induced microscratch.

Determining Tungsten Depths. First, cross-sectioning of multiple microscratches determined that the average scratch depth was approximately 5 nm and that the maximum depth was 10 nm, as shown in the SEM image in Figure 2. Consequently, the target for tungsten removal was set at 15 nm, which is roughly 10% of the bulk tungsten thickness at the metal layer in question.

To achieve a qualitative estimate of the amount of tungsten that was removed, the investigators performed SEM cross sections. In particular, they analyzed the differences in tungsten removal between the wafer center and the wafer edge, isolated and dense lines, and wide and narrow lines. To achieve an in-depth quantitative estimate of tungsten removal and assess the amount of volume material present, metal resistance measurements were performed, since subtle thickness changes in small design rules are difficult to determine reliably on the basis of cross-sectional SEM images.

Process Setup. To perform the plasma etch process, the investigators used two etch chemistries: NF₃ and CF₄. Tungsten removal was performed using an Enviro II dual-chamber resist-strip tool from Ulvac (Methuen, MA), which is primarily employed in postmetal and via etch dry cleaning applications.² This system has two plasma sources: an in situ radio-frequency (RF) plasma source and an ex situ microwave (MW) plasma source. NF₃ and CF₄ cleans were performed using the RF plasma, while an in situ O₂ ash step was performed using the MW plasma.

A 10-second processing time was considered the minimum amount of time necessary to ensure a stable and repeatable plasma. However, at 10 seconds, the NF3 process removed too much tungsten, as confirmed by the cross-sectional image in Figure 3. Besides revealing that the NF3 process removed too much tungsten, the cross section also shows that it attacked the TiN liner too aggressively.

Figure 3: Tungsten removal using the NF3 process for 10 seconds.

Figure 4: Tungsten removal using the CF4 process for 10 seconds followed by an in situ O2 ash step.

As illustrated in Figure 4, the CF₄ option worked very well. It removed tungsten in the required range and did not appear to attack the liner. Tungsten removal was adjusted based on the resistance of the tungsten lines, as shown in Figure 5. With a 10-second etch process time, tungsten line resistance increased by 10% over the process of record (POR) time of 0 seconds. Process parameters such as gas ratios and plasma power were adjusted to optimize the process, but the adjustments had a negative impact on wafer uniformity and process stability.

Figure 5: Tungsten line resistance resulting from CF4 process performed for 0, 10, and 20 seconds. (The circles at the right represent each split group. When they are separate from one another, there is a statistically significant difference among them; 0.05 = 95% confidence interval.)

In addition to performing the in-line evaluation, the investigators analyzed yield data to verify whether the process worked as expected. Since microscratches affect the available redundancy on the DRAM chip, their absolute yield impact can be assessed only on a large number of lots.
To determine the yields of individual wafers, the impact on redundancy of defect sources other than microscratches must be taken into account, because they can cloud the yield results. To assess individual wafer yields, the investigators counted how many redundant elements were used for the bit-line layer on the wafers belonging to the first fully processed split lot. The results of this test are presented in Figure 6. The number of redundant metal lines needed in a functional chip was clearly dependent on the duration of the plasma clean: Fewer redundant elements were required when the tungsten plasma clean process time was increased from the POR time of 0 seconds to 20 seconds. The final process time was selected by balancing the yield benefit, extrapolated from the number of redundant elements, against the increase in line resistance.

Introducing the Plasma Etch Process into the
Manufacturing Environment

After cross-section and parametric data proved the feasibility of the CF₄ process on short-loop wafers and some fully integrated lots, the process was introduced into the high-volume DRAM manufacturing environment. While the production ramp went smoothly and resulted in expected yield gains, high-volume production turned out to be problematic. It was observed that after a larger number of lots were run, particle generation became an issue, as illustrated in the defect-inspection map and related review SEM image in Figure 7. Energy-dispersive x-ray data revealed that the defects were carbon polymers. The problem was solved by adding an in situ ash step to the process sequence.

Figure 6: The number of redundant metal lines needed in a functional chip decreased when the tungsten plasma clean process time was increased from 0 to 20 seconds.

When the ash step was performed before the CF₄ cleaning step, the investigators observed a liner attack, as illustrated in Figure 8. When they performed the ash step after the CF₄ clean, the liner attack did not occur. Instead, tungsten lines appeared, as in the SEM cross section in Figure 4. Apparently, the ash step conditioned the liner in such a way that it could be attacked by the CF₄ etch.

Figure 7: Defect inspection map and SEM review image showing surface particles detected after tungsten etch.

The CF₄ etch–O₂ ash process sequence underwent final testing before it was certified as production-worthy in a volume manufacturing setting. Several production lots were split and processed, half with a proven good slurry batch and half with the quarantined worst-known slurry batch. The wafers were processed together, and then yield data and redundant- element data were analyzed. There was no difference between the split lots, indicating that the etch-back process performed as expected and removed all yield-limiting microscratch-induced shorts.

Process Simplification

Historically, the CMP process at Infineon had been followed by a wet polymer-removal clean process to remove contaminants. After the CF₄ etch–O₂ ash tungsten etch-back process was adopted in volume manufacturing, engineers attempted to simplify the process by replacing the wet clean with a standard spin-rinse dry step. This modification looked promising when the first experiments were conducted, but in the volume production environment, it was seriously flawed. In an analysis of random wafers, the investigators observed that large wafer areas were contaminated with metal-containing polymers that were so thin that they were not detectable in-line by defect inspections. Their existence could be detected only on the basis of their yield impact. Only a transmission electron microscope analysis could identify the residue.

Figure 8: Liner attack (circled areas) observed after the process sequence O2 ash–CF4 etch was performed.

The following hypothesis was used to explain this defect. An inert plasma forming gas (N₂H₂) is used in addition to the active CF₄ to stabilize the plasma. During the etch-back process, WF₆, a gas phase of removed tungsten, and H₂ may be present. Since tungsten deposition is usually performed using WF₆ and H₂ (creating tungsten and hydrogen fluoride), there may be a reverse reaction in the etch-back process that redeposits tungsten onto the wafer.

To verify the hypothesis—and fix the problem—the N₂H₂ forming gas was replaced with N₂ to avoid H₂ availability. But when the process was run with N₂ instead of N₂H₂, the metal-containing polymer was still present. Thus, the hypothesis was proven wrong and the wet clean could not be eliminated.

Conclusion

When microscratches arising from tungsten CMP processing affected device yields, a feasibility study was initiated to evaluate a range of potential solutions: in-line monitoring of the scratches or of shorts in the test structures of the first metal layer, the elimination of the scratches during CMP, and wet and dry etch cleans. Finally, a dry cleaning process was implemented that removes the metal residue from the scratches and prevents them from affecting yields.

With the process being used in volume production, two interesting questions remain: How do the scratches become filled with tungsten during CMP processing? And how do the metal-containing polymer residues form during the tungsten etch-back process? As to the first question, when the
material in the scratch was analyzed, it did not indicate the presence of TiN underneath the tungsten. Therefore, the tungsten had to be backfilled. It is not understood how this happens, especially since tungsten is a very brittle material that is very unlikely to smear into the trench, much as aluminum would do. As to the second question, the initial hypothesis that H2 is needed to form the polymers is incorrect. Another reaction, enabling tungsten-rich polymers to redeposit, seems to take place.

Acknowledgments

This article is based on a paper originally presented at the IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop, held May 4–6, 2004, in Boston. The authors would like to thank those at Infineon who were involved in the challenging but successful introduction of the new tungsten plasma clean process into the fab’s high-volume DRAM manufacturing environment.

References

1. C Dennison, “Developing Effective Inspection Systems and Strategies for Monitoring CMP Processes,” MICRO 16, no. 2, (1998): 31–41.
2. H Xu et al., “Dry Cleaning Technologies for Post Metal and Via Applications” (paper presented at the Symposium on Contamination Free Manufacturing for Semiconductor Processing, Semicon West, San Francisco, July 13–15, 1998).

Heinrich Ollendorf, PhD, is a staff process integration engineer responsible for mid-of-line integration of 140- and 90-nm technology at Infineon Technologies (Richmond, VA). He has been with the company since 1996. Previously, he worked as a research assistant at the Fraunhofer Gesellschaft IWS in Dresden, Germany. Heinrich received a master’s degree and PhD in physics from the University of Heidelberg, Germany. (Ollendorf can be reached at 804/952-6000 or
heinrich.ollendorf@infineon.com.)

Stacey Cabral is a senior process engineer responsible for wet and dry back-end-of-line cleans at Infineon Technologies Richmond, where she has been for four years. Before that, she worked in the printed circuit board industry. She received a BA in chemistry from Hiram College in Hiram, OH, and a BS in chemical engineering from Washington University in St. Louis. (Cabral can be reached at 804/952-6000 or stacey.cabral@infineon.com.)

Robert Fuller is a lead integration engineer for the 300-mm fab expansion start-up at Infineon Technologies Richmond and has been with the company since the 200-mm fab start-up seven years ago. He has 24 years of semiconductor experience and holds 12 patents in various semiconductor fields. He received a master’s degree in physics from North Carolina State University in Raleigh. (Fuller can be reached at 804/952-6000 or robert.fuller@infineon.com.)