EDITOR'S PAGE

Chew on this

Between road time and the recent glut of industry news, I've had a lot of semiconductor manufacturing food for thought to digest. With so many potential trends and interesting stories to chew on, this month's column focuses on several items that have tickled my editorial palate.

Two of the semiconductor playground's big boys have made headlines, though not with the positive spin they might have liked. Both IBM and Intel grudgingly became newsworthy because of their product technology and manufacturing problems. It's one thing if yield or process problems come out in an industry trade mag like MICRO or are discussed over beers in a Hsinchu watering hole, but it's quite another when the bad news hits the mainstream business pages. Remember back in the mid-1990s when AMD's widely reported yield problems while ramping Fab 25 made the papers? It was not a pretty picture and did nothing at the time to enhance perceptions of AMD's manufacturing expertise or build employee morale (although it did play a role in the company's serious embrace of APC/AEC and the subsequent successful ramp of Fab 30).

Intel announced in early May that it was shuttering two of its prize chip development projects, code-named Jayhawk and Tejas. Seems the microchip megacorp could not overcome severe thermal issues with its heretofore successful strategy of ever-scaling single-processor designs. It's not often you can say that Intel couldn't take the heat. So much for the Barrett Bunch's approach of relentlessly ratcheting up the clock rate of its chips. Instead, Intel says it will pursue the so-called "dual-core" processor structure favored by many rival manufacturers, noting that future "cooler" designs should perform better in terms of energy consumption.

Meanwhile, Big Blue claims it has nearly solved the previously reported yield woes experienced on its 130-nm lines. Senior executive John Kelly said the problems were a result of some "interactions" (perhaps lack of interactions?) between certain chip designs and the process technology. Ironically, IBM's Bernie Meyerson revealed the company hasn't seen as many problems in its 90-nm ramp as it has had at the 130-nm node. He also opined that the days of garnering performance benefits from scaling are probably over, since the atomic-level thinness of the gate oxides has led to transistor leakage and rampant power dissipation.

I heard many innovative and practical chipmaking solutions and viewpoints at this year's Advanced Semiconductor Manufacturing Conference in Boston in early May. (Disclaimer: MICRO is the media sponsor of ASMC, so please refrain from flinging those conflict-of-interest charges in my direction.) One of the more intriguing papers presented the results of "extreme-edge engineering" done by a large cross-functional team at Infineon's Richmond, VA, fab.

The team's mission was to reduce the wafer edge exclusion from 3 to 2 mm and convert that additional millimeter of silicon real estate into productive, yielding chips. It turns out that the feasibility study (using mature technology as the test case) not only showed how to get more
devices out of the edge, but also greatly enhanced the overall yield of the former edge-most region of the wafer, an unexpected benefit. The Richmond group's work has not gone unnoticed at corporate: they won a companywide project award, and the results of their efforts have been transferred to other Infineon fab clusters.

You may have noticed that the market researchers have been quite busy counting beans during the past month or two. The forecasters' opinions range from upbeat prognostications that the IC world will maintain its mighty mo' well into next year to Nervous-Nellie predictions of a downturn around the next fiscal corner. For the industry's sake, let's hope the upturn has some legs. One cautionary plea in the spirit of prolonging the good times: chipmakers, please refrain from that crazy double-ordering of equipment that helped trigger the last swoon!

My forecast? Things will be great until they get worse.