In 300-mm semiconductor fabrication there is a trend toward the use of single-wafer postetch polymer wet cleans for copper/low-k polymer stacks. These cleaning steps pose a number of challenges, such as how to successfully clean the low-k stacks without adversely affecting the properties of the low-k film or the underlying materials, and how to mitigate damage to the interconnect metal. For organic low-k films, potential integration problems include the compatibility of clean chemistries with integrated adhesion promoters and excessive swelling of the low-k film itself. The biggest problem facing the interconnect metal is its potential to experience surface corrosion. The successful introduction of porous low-k materials will depend on how effectively these issues can be addressed.

The purpose of the study described in this article was to evaluate the impact of a single-wafer postetch cleaning tool on porous SiLK dielectric resin films manufactured by Dow Chemical (Midland, MI). The article focuses on the relationship between different chemical process approaches and the resulting electrical characteristics of cleaned structures. The electrical test characterization results presented here show that a single-wafer cleaning step, depending on the particular chemistry formulation used, can improve the performance of selected test devices by lowering line resistance (R) and increasing capacitance (C). The data show that an appropriate chemical clean can result in electrical RC product performance that is as good as or better than that of the non-wet-clean process of record (POR).

Experimental Procedure

The test vehicle used in these experiments was a single-damascene structure. The structure consisted of an integrated stack that had a porous dielectric film capped with an SiC/SiO₂ dual hard mask. The minimal lithographic target had a 175-nm linewidth and 0.225-µm spacing. The smallest linewidth was 140 nm. Patterning was achieved using 193-nm lithography combined with an H₂/N₂ reactive ion etch. The postetch trench height was ~100 nm; trench pitch was 3:1. The etch step incorporated an in situ resist removal procedure, thus eliminating the need for a separate resist ash step. The etch chemistry used resulted in the deposition of a protective sidewall polymer, which had to be removed by means of a wet clean.

The experiments were performed on a single-wafer spin processor from SEZ (Villach, Austria). Three different chemistries were investigated for the postetch cleaning step, each representing a fundamentally different approach to residue removal. Chemistry 1 is a commercially manufactured aqueous organic (carboxylic) acid mixture. Chemistry 2, also a commercially manufactured organic mixture, is a more traditional solvent-based product. Chemistry 3 was developed in-house at SEZ using dilute acid ingredients. It was composed of >>99% DI water.

The chemistries' compatibility with the dielectric film was evaluated by determining the characteristics of blanket dielectric films. Their cleaning effectiveness was determined by tilt scanning electron microscopy (SEM) analysis. Based on the results of that analysis, best-known-method (BKM) conditions were ascertained for each chemistry. These BKMs were used for processing blanket and porous dielectric film structures and materials and for probing their electrical properties.

Experimental Results

Processing the Blanket Dielectric Films. After the blanket dielectric films were processed using the three chemistries, a bake step was performed to remove a spurious peak associated with outgassing from the wafer carrier. Then infrared (IR) spectroscopy was conducted to determine whether the films' chemical structure had changed. The IR data indicated that chemical processing did not change the films significantly and did not add chemical species such as water. The physical and electrical properties of the blanket dielectric films are summarized in Tables I and II. The data in the tables are consistent with the target values for porous dielectric films and the IR results.

Table I: Film-thickness variation and adhesion data of porous low-k material after wet clean.

SEM Analysis. Figure 1 presents tilted SEM images of similar serpentine locations on different wafers, illustrating the effects of the different wet clean chemistries on the device structure. Figure 1a, the result of the baseline process, illustrates an as-etched wafer region that received no further postetch treatment. It was apparent that polymer residue had been removed from both the SiCN (hard-mask) layer and the etched porous dielectric film sidewalls. Furthermore, there was no visible evidence that polymeric residue was present on the underlying SiCN layer.

Figure 1: SEM images showing a serpentine structure processed (a) without postetch chemical cleaning, (b) with chemistry 1, (c) with chemistry 2, and (d) with chemistry 3.

There was less sidewall residue on the structures shown in Figures 1b–1d than on the structure in Figure 1a, but in all cases, the sidewalls displayed a significant mottling effect, which was associated with the use of the 193-nm resist. There appeared to be a similar amount of sidewall residue on the wafers processed using chemistries 1 (Figure 1b) and 2 (Figure 1c), and in both cases there was no apparent evidence of residue on the underlying SiCN layer.

While the wafers processed using chemistry 3 displayed somewhat less residue on the porous dielectric film sidewalls and SiCN layers than did the wafers processed using chemistries 1 and 2, there was an artifact on the underlying SiCN layer that is clearly visible in Figure 1d. That artifact had two possible origins. First, chemistry 3 could have reacted with the SiCN layer, causing bubbling or delamination. However, given the nature and concentrations of the components in chemistry 3, that explanation is highly unlikely, since the mixture did not react noticeably with any of the underlying films. Second, the artifact could have been caused by polymer residue located on the SiCN surface at the bottom of the trench. Since that residue could not have been deposited by the chemical filtration and dispense system used in the experiments, it was concluded that a uniform residue, not readily apparent in the SEM image in Figures 1a–1c, was present on the open areas of the underlying SiCN film. Under the given process conditions, that residue had been attacked and partially removed by chemistry 3. Visual evidence provided by SEM analysis and supported by subsequent parametric data substantiates that conclusion.

Parametric Evaluation. Figure 2a shows the cumulative resistance distribution of a 2850-cm-long M1 serpentine with a 0.175-µm line and 0.225-µm space, while Figure 2b shows the cumulative resistance distribution of a 0.32-cm-long isolated serpentine with a 9.0-µm line and a 1.0-µm space. The data presented in these figures are consistent with the effects of the different chemistries shown in the SEM images in Figure 1. While there is a barely distinguishable difference between the data for wafers processed using the baseline chemistry and chemistry 2, indicating that they did not remove sidewall polymer during wet cleaning, the data for the wafers processed using chemistries 1 and 3 show a clear decrease in line resistance, reflecting their ability to remove the sidewall polymer. Chemistries 1 and 3 outperformed chemistry 2 because they were also able to remove the residual polymer from the bottom of the SiCN trench, thereby maximizing the copper line cross-sectional area.

Figure 3: Relative resistance change as a function of residue thickness.

The relative effect of overall polymer residue on line resistance is shown in Figure 3. Based on an analysis of median resistance values derived from the electrical data in Figure 2a, a decrease in resistance of approximately 6% was observed, corresponding to a sidewall polymer thickness of approximately 4 nm. That estimate is similar to the actual residue thickness that was measured during cross-sectional analysis.

Interline capacitance data from 400-µm-long comb fingers with a 0.175-µm line and a 0.225-µm space are presented in Figure 4. In general, the more polymer residue that was removed, the more capacitance increased. The chemistries that had the greatest impact on line resistance—1 and 3—also had the greatest impact on capacitance. Capacitance on the wafers that had been processed using chemistries 1 and 3 was 6% greater than that on the wafers processed using the baseline application or chemistry 2.

Figure 4: Interline capacitance of 400-µm-long comb fingers with a 0.175-µm line and a 0.225-µm space.

To investigate the effect of polymer residue on capacitance, a 2-D Raphael simulation model was built. Figure 5 presents the results of that simulation for the wafers that were processed using chemistry 3, which removed residue from the sidewalls and bottom of the trench. While the Raphael simulation model did not permit the investigators to determine the precise k-value of the polymer residue within the model's error limits, it did show that a relative change in capacitance of 6% corresponded to the removal of approximately 3 nm of polymeric residue from the sidewalls and bottom of the device structure. Despite the model's limitations, that value was within the model's expected error range and matched actual residue-thickness measurements.

Figure 5: Simulated capacitance change as a function of residue thickness.

Finally, RC line delay was computed using the line resistance and interline capacitance data obtained for each chemistry. As illustrated in Figure 6, chemistry 3 provided the lowest RC delay, which was consistent with resistance and capacitance results and was within the error limits of the measurements.

Conclusion

This article presents the results of experiments to determine the effects of single-wafer cleans on porous dielectric-film wafer stacks. It demonstrates that the physical and electrical properties of selected devices containing porous low-k material can be improved by using an appropriate wet cleaning chemistry to remove post-dry-etch residue. Furthermore, it shows that an in-house dilute-acid cleaning mixture appears to result in equivalent or better device performance than commercial organic mixtures. The in-house formulation also provides an unmatched cost of ownership.

Figure 6: RC delay, computed using the line resistance and interline capacitance data for each chemistry.

The cleaning efficiency of the in-house chemistry resulted in the removal of polymer residue from sidewalls and the bottom of trenches. From both physical and parametric electrical analysis, it was determined that a 3- to 4-nm layer of polymer residue present on the sidewalls and bottom of the trench was effectively removed, resulting in improved overall RC performance. The observed change in the cross-sectional area of the device structures was sufficient to account for the improvement in electrical resistance and capacitance values.

In conclusion, the method described here provides customers with a means to derive greater value from the use of SiLK dielectric resin.

Acknowledgments

The authors would like to express their appreciation for the support provided by Steve Rozeveld, Elvin Beach, and Charlie Wood at Dow Chemical Analytical Sciences. They would also like to thank Gale Hansen of SEZ for generating the SEM data presented in this article. Special thanks go to Brent Ames, Frank Tolic, and Vangie Lopez at International Sematech's wafer services for the electrical test data discussed here.

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Leo Archer, PhD, serves as director of emerging technologies at SEZ in Phoenix. He joined SEZ America in 1999 as the lead process engineer responsible for the development of a new hybrid cleaning product. Appointed senior technologist in 2002, he furthered SEZ's work with low-k materials and etch-residue removal applications. Before joining the company, Archer worked for Intel and TI in the CMP area and on novel device development and advanced cleaning processes. He has written many papers and articles for scientific and industry publications. He received a BS in chemistry and a PhD in inorganic chemistry from the University of New Mexico in Albuquerque. (Archer can be reached at 602/453-5023 or larcher@us.sez.com.)

Joost Waeterloos, PhD, is responsible for leading the integration of advanced materials and the coordination of research consortia programs at Dow Chemical, which he joined in 1998. He has published more than 45 papers in the field of low-k integration, holds four patents on copper dual-damascene architecture, and has written a book chapter on integration. Waeterloos received a master's degree in electrical engineering in 1991 and a master's degree in microelectronic engineering in 1994 from the University of Leuven, Belgium. In 1998 he received a PhD from the University of Leuven for research on integration of low-permittivity dielectrics in advanced interconnect technologies. (Waeterloos can be reached at +32 476 313086 or jwaeterloos@dow.com.)

Michael Simmonds, PhD, joined the advanced electronic materials business unit of Dow Chemical in 1997 and has been leading projects to evaluate new polymers for electronic applications. In 2001, he was appointed SiLKnet Alliance development manager. Simmonds has held several positions at Elf Atochem, the Swiss Center of Microtechnology, and Dow Chemical focusing on the application of new materials to a variety of high-tech fields. His work has been published in the scientific and patent literature, and he is also the author of a book chapter. Simmonds received a bachelor's degree in chemistry from the University of Surrey, Guildford, UK, in 1988. In 1993, he received a PhD based on his advanced studies in the area of low-temperature aluminum chemical vapor deposition, which he carried out at the Center for Interfacial Engineering with support from the University of Minnesota in Minneapolis. (Simmonds can be reached at +11 411 7282642 or msimmonds@dow.com.)

Brent Ames has managed the sales and marketing group of the advanced technology development facility at International Sematech for the past four years. He has worked in Sematech's CVD, etch, photolithography, and diffusion divisions for seven years. Before beginning semi- conductor research at Sematech, Ames worked for the IBM RISC 6000 division. He received a bachelor's degree in business management from St. Edwards University in Austin, TX. (Ames can be reached at 512/356-7021 or brent.ames@sematech.org.)

Frank Tolic heads wafer services back-end product integration at International Sematech. Previously, he worked as project manager for technology transfer of copper low-k with a member company and as product engineer for interconnect thrust for Sematech. Before that, Tolic worked for GM, Ford, and Chrysler. Additionally, he worked at Motorola for seven years as a device engineer in the advanced products research and development laboratory, which included work on the first copper-based IC product. The coauthor of several industry papers, he received bachelor's degrees in electrical engineering and mechanical engineering from Lawrence Tech University in Southfield, MI. (Tolic can be reached at 512/356-3340 or frank.tolic@sematech.org.)

Ketan Itchhaporia worked for Dow Chemical as an application development and technical sales engineer for spin-on dielectric materials until February 2004. Previously, he held positions as a senior process development engineer and technical sales engineer at FSI International in the area of coater/developer and spin-on dielectric tracks equipment. Itchhaporia has more than 14 years of experience in semiconductor manufacturing, including experience in bringing products from concept to production, conducting equipment process demonstrations for customers, and sales and production support. He received a bachelor's degree in chemistry (industrial electronics and electrochemistry) from the Gujarat University in Ahnedabad, India, and completed a business management program at the H.B. Institute of Communication & Management in Ahnedabad. (Itchhaporia can be reached at 510/468-9359 or gkfly@aol.com.)