Investigating the impact of backside defect inspection on process development and yields

Chandra Saravanan, Zhuan Liu, Weidong Yang, Matthew F. Swisher, and Anlun Tang, Nanometrics

Shrinking device dimensions place aggressive demands on defect detection metrology. As device density and critical dimension (CD) uniformity requirements become more stringent, the maximum potential of lithography can be exploited only if the quality of the incoming wafer is not compromised. The section on difficult lithography challenges and the resist requirements tables of The International Technology Roadmap for Semiconductors (ITRS) stipulate that the industry should be able to detect 40-nm front-surface defects by 2007 and <30-nm defects after 2010. Based on backside depth-of-focus (DOF) considerations, 100-nm backside defects should be detectable by 2007 and 50-nm defects should be detectable after 2007.¹

Nearly all processes in a wafer fab can cause backside contamination. In-tool wafer-handling systems such as robot arms and chucks, cross-contamination resulting from wafers as they pass from tool to tool, and wafer-handling systems such as lot boxes are sources of backside contamination. Backside defects (particles or scratches) can create local distortions on the wafer, causing DOF issues that result in lithography focus spots. In smaller device features, the lithography focus-spot problem is exacerbated because of smaller DOF and tighter CD uniformity requirements.

In addition to these issues, particles on the wafer backside can adhere to the chuck, creating cascading focus spots on multiple wafers or lots, requiring photoresist rework and loss of throughput. Backside defects can also cause frontside contamination on wafers in lot boxes. Because focus spots and frontside defects result in considerable yield loss, defect excursions in the fab should be monitored carefully.^2,3

Backside Defect Inspection

The wafer backside poses severe challenges for defect metrology. First, detecting particles on 200-mm wafers is difficult because of the wafers' rough backside surfaces. Wafer roughness physically limits the particle sizes that can be detected on the wafer (for example, particles in crevices and cracks cannot be detected). Another challenge is the separation of added defects from the inherently rough features of the wafer backside. Second, the front- and backsides of production wafers must be handled nondestructively in metrology tools. Third, market pressures demand high throughputs and a low cost of ownership. Fourth, particle migration from the edge toward the center of the wafer can be exacerbated by the 2–3-mm edge exclusion feature that is typical in many particle and defect-detection tools. Finally, early detection and correction of defects using process control methods
require metrology-tool integration.

To address these issues, the NanoUDI from Nanometrics (Milpitas, CA) was installed in a wafer fab to perform front- and backside defect inspection of 200-mm wafers. Tests were also performed to determine the effects of backside defect detection on process development and yield enhancement.

The 300-mm-capable instrument uses broad-band polarized light for dark-field imaging, and it uses image-processing techniques to detect defects and remove background and noise. The light incidence angle and polarization are optimized to increase the signal-to-noise ratio, depending on the wafer type and surface roughness. The tool can detect particles on bare silicon, blanket films, patterned wafers, monitor wafers, physical vapor deposition seed-copper films, electroplated copper, and surfaces that have undergone chemical-mechanical planarization (CMP). The tool has no edge exclusion and uses edge-gripping technology for nondestructive wafer handling. The fab tests demonstrated that in an integrated setup, the tool's through-
put is ~180 wafers per hour.

Backside Inspection Applications in a Wafer Fab

Solving lithography focus-spot problems involves detecting and eliminating both systematic and random defects. Throughput and yield loss arising from photoresist rework, chuck contamination, and focus spots can be reduced considerably using backside defect metrology. Systematic sources of defects can be isolated and eliminated by segmenting wafer process routes. Throughput and yield loss can also be avoided by monitoring the wafer backside for random defects and process drifts.

The tests discussed here involved multiple inspection steps for several backside applications, including CMP, scrub, nitride and oxide deposition, and lithography. Measurements were taken before and after processing.

Figure 1: Wafer scan showing systematic defects from three wafers from one lot.

For several critical lithography steps in which small-CD features are printed, systematic backside inspections were performed. Prelithography stages were further segmented so that defect inspection could be performed before and after both sides of the wafer were scrubbed. Depending on the prelithography stage, defect inspections were also performed before and after a CMP step that was followed by a scrub.

First, multiple wafers and lots from the fab production line were sampled. Several systematic defects and significant numbers of random defects were always found on the backside of each wafer. Figure 1 shows a composite of detected defects from three selected wafers from a lot. The figure shows random particles and systematic defects such as edge-bead removal rings, robot-arm signatures, chuck marks, deposition-tool marks, and scratches near the wafer notch.

Figure 2: Backside defects after a wafer scrub.

Then the dark-field inspection system was used to qualify fab scrubbers. Figure 2 illustrates a postscrub defect scan of the same wafers shown in Figure 1. While the robot-arm signatures were largely removed, many other systematic defects and random particles remained on the wafers. That result was found to be the case for all lithography steps. In addition, pre- and post-scrubbing data from various prelithography steps showed that there were large variations in scrubber efficiency. The scrubbers under investigation removed anywhere from 10 to 80% of the particles on the wafers. For example, Figure 3 presents the percentage of defects removed from six wafers from two lots that had been scrubbed using a particular tool. Only 12.5% of the total defects were removed.

Figure 3: Percentage of particles removed by a particular scrubber. Only 12.5% of the total defects were removed.

Defect adders were also detected after a series of lithography steps performed on photoresist spin deposition, alignment and exposure, and developing tools. The postdevelop inspection of six random wafers in a lot indicated a total count of more than 200 particles with sizes ranging from 0.5 to >40 µm, as illustrated in Figure 4.

Lithography focus spots are caused by local wafer distortions. Typical steppers and scanners incorporate flatness-monitoring tools that report errors when topographical distortions are encountered.⁴ To establish a correlation between frontside lithography focus spots and flatness-
monitoring-tool errors caused by backside wafer defects, defect scans were performed on wafers with lithography focus spots.

Figure 4. Defect adders during the lithography stage. For six wafers, more than 200 adders were counted.

Two types of lithography focus spots, cascading and noncascading, were found on wafers from the fab's production line. While the dark-field inspection tool detected cascading lithography focus spots caused by particles on the chuck at exactly the same locations on multiple wafers from different lots, it did not detect particles at corresponding locations on the wafer backside. Noncascading focus spots, on the other hand, appeared only on isolated wafers, but these systematic or random defects were always detected at corresponding locations on the wafer backside. These data demonstrate that there was a 100% correlation between frontside lithography focus spots or flatness-monitoring-tool errors and local wafer distortions caused by backside defects.

Figure 5: A typical focus spot (a) and a corresponding systematic backside defect (b) detected by the dark-field inspection tool.

Some lithography focus spots consistently appeared at certain locations near the wafer edge. After the backside of wafers with these defects was examined, it was determined that these focus spots were the result of systematic defects caused by nitride and oxide deposition marks. Figure 5a illustrates a typical focus spot of this type, while Figure 5b shows the corresponding backside defect.

The impact of backside polishing on frontside lithography focus spots was studied by splitting a wafer lot into two halves, one of which underwent single-side polishing (SSP) and the other double-side polishing (DSP). This test showed that the DSP wafers were more prone to focus spots than the SSP wafers. While particles tend to disappear into the rough backside surfaces of SSP wafers, they tend to be prominent on the smooth backside surfaces of DSP wafers, creating a higher risk of lithography focus spots.

Backside Defect Monitoring for Process Development and Yield Enhancement

Yield loss in lithography applications drives the need for backside inspections. The elimination of backside defects allows wafers to be flattened locally and removes DOF issues. To reduce yield loss, wafer fabs must minimize these problems by isolating defect sources and modifying processes.

Figure 6: Backside nitride defects (red circles) and oxide defects (yellow circles) after unmodified nitride and oxide deposition (a); and backside defects after modified nitride and oxide deposition (b). The modified process removed most of the nitride deposition marks.

Based on backside inspection results from the dark-field inspection tool, process and tool modifications were carried out. For example, nitride and oxide deposition processes were modified in order to reduce systematic defects on the wafer edge that correlated strongly to several lithography focus spots. The scan in Figure 6a shows backside defects from three wafers that underwent ordinary nitride and oxide deposition, while the scan in Figure 6b shows backside defects on wafers from another lot that underwent modified nitride and oxide deposition. The modified processes clearly resulted in reduced numbers of nitride deposition marks.

Figure 7: Backside defects, including oxide deposition marks (circled), after oxide deposition without a scrubbing step (a); and backside defects after oxide deposition with a scrubbing step (b). The postoxide scrub reduced the number of oxide deposition marks substantially.

Another process modification was performed to test a new scrubbing step following nitride and oxide deposition steps. As illustrated in Figure 7a, many oxide deposition marks were found after a scrubbing step following nitride deposition. It is very likely that the oxide marks were covered by the much harder nitride materials and were therefore difficult to remove. When a scrubbing step was performed after oxide deposition, the number of oxide deposition marks was reduced substantially, as shown in Figure 7b.

In the fab the tool was used to qualify product wafers at the scrub stage preceding lithography. And at the postlithography stage, the tool can indicate that a chuck clean or a photoresist rework cycle is necessary if contamination from the chuck is detected. The tool also serves to qualify scrubbers during routine process stream and scrubber maintenance. To test for defect adders on the front- and backside of a wafer, two test wafers are typically needed. In contrast, the dark-field tool can inspect both the front- and backside of test wafers after a double-sided scrub. In addition, the inspection tool can detect backside deposition marks, indicating that nitride and oxide deposition tools require maintenance.

Conclusion

Wafer backside inspection using a dark-field imaging tool can detect significant levels of backside defects, including random particles and a range of systematic defects. In fab tests, such backside defects were found to cause frontside focus spots or flatness-monitoring-tool errors in steppers and scanners, leading to yield and throughput loss in semiconductor device manufacturing. To avoid lithography focus spots or tool errors, routine backside defect inspection, as well as process and tool performance monitoring and modifications, are becoming more and more important. As device sizes continue to shrink and stringent DOF requirements place strict constraints on allowable backside defects, wafer backside defect metrology will play an increasingly important role in lithography.

Acknowledgments

The authors wish to thank UDI team members Mang Chau, David Zhu, Yongkang Wang, Cathleen Hyles, and Barry Bowman for their contributions to the work described in this article. They are also grateful for the collaboration of Edmund Symalla, Tony Daniel, and Marcus Fields.

References

1. The International Technology Roadmap for Semiconductors (San Jose, Semiconductor Industry Association, 2003): available from Internet: http://public.itrs.net.

2. L Cheema et al., "Yield Enhancement from Wafer Backside Inspection," Solid State Technology 46, no. 9 (2003): 57–60.

3. PS Lysaght and M West, "Addressing Cu Contamination via Spin-Etch Cleaning," Solid State Technology 42, no. 11 (1999): 63–70.

4. Y Zhang et al., "Wafer Mapping for Stepper Effects Characterization," in Proceedings of SPIE: Metrology, Inspection, and Process Control for Microlithography XIII, vol. 3677 (Bellingham, WA, SPIE, 1999), 250–254.

Chandra Saravanan, PhD, is an applications scientist at Nanometrics (Milpitas, CA). In addition to developing applications and algorithms for advanced metrology systems, he is involved in defect inspection, diffraction-based overlay technology, and residue detection. He received a PhD in theoretical chemistry at the University of Massachusetts, Amherst, in 1999. He also spent two years as a postdoc in the chemistry department at the University of California, Berkeley. (Saravanan can be reached at 408/435-9600, ext. 292, or csaravanan@nanometrics.com.)

Zhuan Liu, PhD, is an applications scientist at Nanometrics. He is involved in the development and applications of the company's new technologies, including universal defect inspection and CMP residue detection. He also participates in applications projects in the area of thin-film and optical CD metrology. He received a PhD in chemistry from Cambridge University, UK. (Liu can be reached at 408/435-9600, ext. 297, or zliu@nanometrics.com.)

Weidong Yang, PhD, is an applications scientist at Nanometrics, where he develops algorithms for advanced metrology. He has authored or coauthored more than 30 papers in the fields of physics and engineering. He received a PhD in physics from the University of Oregon (Eugene) in 1999. (Yang can be reached at 408/435-9600, ext. 237, or wyang@nanometrics.com.)

Matthew F. Swisher is a systems technician in Nanometrics, where he is involved in the development and release of new technologies, including in the field of universal defect inspection and optical CD metrology. He has more than six years of industry experience in mechanical, electrical, and systems areas. (Swisher can be reached at 408/435-9600, ext. 276, or mswisher@nanometrics.com.)

Anlun Tang, PhD, is a scientist at Nanometrics, where he is responsible for R&D in the area of micro- and macrodefect inspection systems. He received a BS in physics from Northwestern University in Xian, China, and a PhD from Kent State University in Kent, OH. (Tang can be reached at 408/435-9600, ext. 280, or atang@nanometrics.com.)