METROLOGY:

Pressures Build on Tool Performance

Shrinking feature sizes, tighter control of device electrical parameters, such as threshold voltage and leakage current, and new interconnect materials will provide the main challenges for physical metrology methods." So says the metrology chapter in the latest International Technology Roadmap for Semiconductors (ITRS). The demands on metrology and inspection equipment will become increasingly stringent with each successive process node. For this installment of The Hot Button, we asked experts what they thought the critical issues were in the metrology area, and why.

RONALD REMKE (metrology program manager, International Sematech Manufacturing Initiative): As noted under "Difficult Challenges" in the yield enhancement chapter of the 2003 ITRS, the hot-button issues in patterned-wafer metrology and inspection/
review include detection of shrinking yield-critical defects, high-aspect-ratio defects, and nonvisual defects.

Nonvisual defects represent a large percentage of the causes of yield loss at electrical test.  –Ron Remke

As circuit layout dimensions continue to shrink, the yield-impacting defect size decreases, requiring inspection tools to detect these smaller defects and improve sensitivity. However, the required improved tool sensitivity must be balanced against lower tool throughput and higher tool cost of ownership (COO). In addition, the distinction between acceptable process variation and yield-critical defects is becoming blurred. High-aspect-ratio inspection (HARI) continues to be a difficult challenge because of the signal noise and scattering associated with the transmission and detection of energy in high-aspect-ratio structures like vias and contacts. Electron-beam inspection tools offer one solution to HARI, but at slower scan speeds and a higher COO.

Nonvisual defects are defined as defects that can be detected electrically but either have no detectable physical remnant or are too small to be detected with current in-line defect inspection tools. A survey of International Sematech member companies indicated that these nonvisual defects represented a large percentage of the causes of yield loss at electrical test. For defect review, the speed and accuracy of automated defect classification continues to be an issue.

BILL GATELY (general manager, Philips Advanced Metrology Systems): The move to copper interconnects has created a tremendous number of issues for IC device makers, and these issues are increasing with the additional incorporation of low-k dielectric materials.

One thing that must be appreciated about copper damascene is that the process is considerably more complex than aluminum. As we all know, you cannot etch fine patterns in copper. Thus, copper processes, unlike aluminum, have pattern-specific issues. The uniformity of critical steps such as electroplating and CMP depend very much on the local feature geometry on the die. For instance, film thickness can vary greatly between solid areas and fine-line arrays, depending on the level of electrochemical deposition overburden as well as CMP dishing and erosion. Furthermore, the uniformity of the final result depends critically on the interplay of the various processing steps.

Cost-effective metal film metrology is needed on the production line.  –Bill Gately

Equipment makers have worked hard to control these effects through more-advanced processing techniques. However, in order to characterize new processes and keep developed ones running smoothly, cost-effective metal film metrology is needed on the production line. What makes copper different is the requirement for metal film thickness measurement directly on product wafers—to catch problems that appear only on patterns.

A significant question, though, is how much metrology is needed—and at what cost? We see many device manufacturers taking different approaches to this question. Some look at copper thickness metrology primarily as an engineering and development tool not needed on the fab line. Those at the leading edge of high-volume copper manufacturing are moving toward deploying large amounts of metrology and integrating copper measurement into their advanced process control.

Low cost per wafer enables the high-volume advanced process control approach. We believe that as copper becomes a bigger part of the industry's total output, there will be a convergence in the semiconductor industry toward greater in-line wafer sampling. This can only be achieved if there is a practical low-cost-of-ownership technique available for in-line metal film measurement.

OLIVER PATTERSON (member of technical staff, Agere Systems): As process margins decrease, systematic yield loss will become an even larger factor than it is today. Incorporation of systematic test structures that can be tested in-line using voltage contrast could be very useful to address this concern. Voltage contrast is preferable to probe-able structures because in-line probes introduce defectivity and the space required for pads can be quite substantial. Some test structures would monitor photolithographic performance in the face of topography variation across the wafer and over time caused by CMP and other factors. Others could monitor gate oxide integrity, for example. Certainly development of an effective library of these test structures is a hot-button issue. This technique can be used to more quickly ramp a process as well as monitor for process excursions that previously may only have been detected with substantial yield data.

Why don't review tools have the ability to classify defects as killers and nonkillers yet?  –Oliver Patterson

The ability to detect defectivity in high-aspect-ratio features such as contacts and trenches is another area of critical need. SEM inspection tools are very effective at finding opens using voltage contrast inspection. Unfortunately, only some product features show a voltage contrast signal, and random defectivity test structures require a large area. When a voltage contrast defect is found, a cross section is generally necessary to determine or at least verify the root cause. SEM inspection tools can also be used to detect defectivity in unfilled HAR features; however, this type of inspection takes a relatively long time and is expensive. Furthermore, the number of nuisance defects can be overwhelming. Substantial process is needed in the development of cost-effective tools capable of HARI.

A third area of need is better automated defect classification algorithms. Why don't review tools have the ability to classify defects as killers and nonkillers yet? It's fundamental to our business to be able to focus on what's limiting yield. It should be relatively simple to determine the yield impact of a defect by incorporating some simple analysis of the image background. For example, does a metal extra bridge two metal runners or not?

KEVIN MONAHAN (vice president of technology, patterning solutions group, KLA-Tencor): Hidden profile errors in device structures are contributing more significantly to yield loss. As a result, we are seeing a second trend toward the use of spectroscopic ellipsometry (SE) for in-line CD and profile metrology.

Semiconductor manufacturers also want to monitor CDs and profiles directly on production wafers, avoiding destructive and costly off-line analysis. Responding to this need, optical film thickness platforms based on spectroscopic ellipsometry have been adopted to provide simultaneous in-line monitoring of CD, sidewall angle, depth, and film thickness. Typical applications of SE profiling technology include the complex stacks and layouts associated with shallow-trench isolation, multilayer gate structures, sidewall spacers, and contact arrays. At one time, the applications to sidewall spacers and contact arrays were thought to be a difficult challenge, but these problems have been solved.

Contacts are an especially important application because of the association of small, sloped, or footed openings with yield loss. The low static noise floor (~0.1 nm) of the SE system enables precise measurement of faceting and footing in addition to CD. The low dynamic noise floor (~0.2 nm) enables accurate intrawafer and wafer-to-wafer comparison. Both elliptical and rectangular contacts can be measured in any orientation, and virtually any "hole element" can be measured and used for process control. In addition, a variety of rectangular, triangular, and paired layouts are now supported.

JON OPSAL (chief technology officer and vice president of research, ThermaWave): One of the most critical issues is the ability to measure complex films, multilayer film stacks, and periodic structures in small boxes on the product (patterned wafers). Why? Because technology shrinks require new films and smaller features.

Take the evolution of gate dielectrics from thermal oxide to nitrided oxide. What was once a measurement that required high precision for thickness that was satisfied by a single measurement technology has become a high-precision measurement for thickness and nitride content that requires multiple technologies to provide the information needed for process control. The move to 300 mm has made the cost of test wafers prohibitive, driving the demand to measure on product wafers where test structure space is limited.

As another example, the move to smaller geometries also requires new methods for measuring structures that are beyond the reach of the CD-SEM. The most promising approaches for high-volume production monitoring are turning out to be optics-based (broadband spectroscopic reflectrometry and ellipsometry), which show potential down to the 45-nm node for measuring both films and structures.