Power management applications are relying increasingly on highly integrated bipolar-CMOS-DMOS (BCD) processes, combining bipolar and logic components with large metal-oxide-semiconductor (MOS) drivers on the same chip. As processes become more complex and customers on short time-to-market schedules seek a strategic advantage over their competitors, fabs must identify and resolve process issues quickly during preproduction.

This article discusses the PBC4 process at PolarFab (Bloomington, MN) and identifies a gate oxide (GOX) leakage issue that occurred in a large MOS driver during the process qualification and transfer phase. The investigation process and the final identification of first metal etch as the culprit process step is described in detail. Finally, the article discusses the results of the investigation and the solution that was implemented to reduce leakage levels in MOS devices.

The PBC4 Process

PolarFab's PBC4 process is one of many available BCD processes, which monolithically integrate dense, low-voltage CMOS and bipolar control circuitry with power DMOS transistors. PBC4 is a 0.5-µm, 40-V process that provides a versatile platform for applications requiring BiCMOS-only or BCD process technologies.

The process integrates dense 0.5-µm CMOS with high-voltage drivers, enabling the fabrication of complex smart-power chips, and offers low specific-on-resistance (Rsp) N-channel MOS devices at 13.2- and 30-V nodes. PBC4 features dual gate oxides (5.5 and 16 V), complementary N- and P-channel MOSFETs with 5-, 16-, and 30-V capabilities, vertical NPN and lateral PNP bipolar transistors, a variety of passive elements, and an NMOS device rated for 40-V operation. The process is suitable for a wide array of smart-power and power-management ICs in applications such as motor controllers, gate drivers, and microprocessor supervisory circuits. Detailed technical information on the PBC4 process is available in the literature.^1,2

Figure 1: Cross-sectional schematic of the DR3 driver (NMOSTUBMDD design). Driver areas include the epitaxial layer (EPI), the isolation (ISO), the n+ and p+ (NPL and PPL) implant regions, the n-field (NFD), the n- and p-tub (NTB and PTB), the channel stop (CHS), the n- and p-type lightly doped drain (NLD and PLD) implant regions, the n-buried layer (NBL), and the polysilicon layer (POL).

PBC4's four large NMOS drivers, DR4, DR3, DR2, and DVOC, are based on the NMOSTUBMDD design illustrated in the cross-section diagram in Figure 1. NMOSTUBMDD is a 16-V asymmetric NMOS device designed for large digital switches. Relying on a 400-Å-thick GOX, it has a 2-µm polysilicon gate length, a 1.14-V threshold voltage, and 69-mΩ X mm² Rsp (measured at a gate-to-source level of 12 V). All four devices have identical active and gate areas—on the order of 660,000 and 250,000 µm², respectively—and have pads connecting their gate, drain, and source terminals. The only difference between the drivers is that their metallization layers are configured differently.

Figure 2: Top view of the PACMAN4X technology qualification vehicle, including the four NMOS drivers (DR4, DR3, DR2, and DVOC) and the LPNP current-mode logic block.

Identifying Gate Oxide Leakage Failure during Qualification

Successfully transferring any process from R&D to manufacturing requires process qualification, which is achieved in part by the design and use of a technology qualification vehicle. Developed to fully qualify the two-metal-layer, 6-in. version of the PBC4 process, the PACMAN4X technology qualification vehicle is a 100 X 140-mil test chip that consists of a variety of subcircuits. As illustrated in Figures 2 and 3, the subcircuits include a lateral PNP current-mode logic inverter string of 453 differential pairs; large and small Schottky diodes; four large NMOS drivers; a variety of electrostatic-discharge structures; and metal, top metal, and polysilicon comb structures. In addition to PACMAN4X, other, more-complex technology qualification vehicles are used to qualify new devices and perform PBC4 process monitoring.

Figure 3: Top view schematic of the PACMAN4X technology qualification vehicle.

Because the four NMOS drivers account for about 28% of the die area of the PACMAN4X technology qualification vehicle, they were expected to be the most sensitive structures to defects. And because these devices have large active areas, it was expected that most failures would be related to GOX leakage. Indeed, initial test results during the qualification phase revealed GOX leakage failures in the large NMOS devices, which were the dominant yield detractors.

Beginning with the DR4 device and followed by the DR3, DR2, and DVOC devices, all four drivers were functionally tested. The most common failure mode in low-yielding lots was GOX leakage in the DR3 device (represented by most of the functionals in Figure 4). As illustrated in the wafer maps in Figure 4b, the GOX leakage failures appeared as crescent-shaped patterns.

Figure 4: Sample DR3 GOX leakage wafer maps for (a) good and (b) bad lots.

Discovering Pinholes in the GOX during Failure Analysis

Failure analysis was performed to identify where the failures were occurring on the DR3 device. The first step was to use liquid-crystal analysis to identify defect locations, mark the relative location(s) of the hot spot(s), and parallel lap down to the polysilicon layer. To highlight defects, which appeared as holes in the oxide layer, a solution of potassium hydroxide (KOH) was used to etch away the polysilicon layer without damaging the GOX layer. The etch step revealed oxide pinholes at the locations identified by the liquid-crystal method.

SEM analysis revealed a pinhole with a diameter of <0.05 µm at the location of the hot spot. As shown in Figure 5, the pinhole had a square-shaped appearance, which resulted from the KOH etching characteristics of single-crystal silicon. However, SEM analysis did not provide any clues as to what was causing the defect. In most cases, liquid-crystal analysis followed by KOH highlighting reveals the location of the defect but not its cause. The current applied during liquid-crystal highlighting destroys the original defect, leaving damaged oxide and sometimes damaged silicon.

Figure 5: SEM image of the oxide defect identified during failure analysis. The pinhole defect is not visible with polysilicon covering it.

In-line defect analysis, including the scanning and review of patterned wafers, was performed in the GOX process module to identify defect issues. However, no credible evidence was found to explain the GOX leakage.

Possible Causes of DR3 Failure

Previous experiments had already shown that the high failure frequency of the DR3 device was not a result of the order in which the drivers were tested. Therefore, five other explanations were considered.

GOX Integrity. GOX integrity was considered and evaluated even before failure analysis was performed. The parametric structures on the chip that tested the integrity of the 400-Å GOX layer did not indicate problems. Several wafers were mapped for GOX leakage. The gate area of these parametric structures was approximately 100,000 µm². Initially, it was thought that the parametric structure did not indicate failures because its area was smaller than that of the DR3 driver's active area. In order to eliminate the gate area as a possible defect suspect, another capacitor structure with a gate area similar to that of the DR3 structure was tested. No GOX failures were observed.

Plasma Charging. Since most of the failures involved the DR3 driver, plasma-charging issues were considered a plausible root cause of the oxide defects. Hence, antenna ratios were calculated for all four driver structures. Because of the drivers' large gate area, antenna ratios were well within PolarFab's design specifications (100:1). Moreover, only small antenna-ratio differences were observed among the four drivers.

Implant Defects. It was conceivable that defects in the silicon generated during n-tub implant were responsible for the oxide defects. Moreover, because there was no thermal anneal step prior to the growth of the epitaxial layer, it was plausible that these defects appeared in the epitaxial layer and manifested themselves as GOX defects. This theory was substantiated to some extent by failure analysis findings showing that most of the defects were located in the n-tub area.

Resist Coat and Strip Steps. Because the resist was coated twice on the thick 400-Å GOX to create the thin oxide devices, it was conceivable that the defects were a product of the resist coat and strip steps. An incomplete resist strip can result in GOX defects.

Spray Acid Tool. In a previous technology, it was observed that when the substrate under the GOX layer had been heavily doped and then resist strips were performed in a spray acid tool, GOX defects were generated. Unlike the previous technology, PBC4 did not have a heavily doped substrate; nevertheless, resist strips performed in the tool were identified as a possible source of the DR3 failures.

Several corrective measures were taken to test these hypotheses: defect inspections were conducted after resist strips on the GOX layer, an anneal step was added prior to epitaxial growth, the resist step on top of the GOX layer was eliminated, and resist strips in the spray acid tool were ceased. However, none of these measures resulted in the identification of the root cause failure. Thus, further investigation was needed.

Tool Commonality Analysis Incriminates First Metal Etch Step

Since many lots had been fully processed through the fab by the time the qualification phase was well under way, enough data were available to warrant the initiation of a tool commonality study. While the initial study did not offer significant clues about the origin of the DR3 GOX leakage, further analysis uncovered the existence of a bimodality (better and poorer wafers) in the bad lots.

Figure 6: DR3 gate leakage failures by lot and wafer.

Figure 6 presents the results of a driver gate leakage failure test showing DR3 failures by wafer and lot. This test was performed by grounding the source, drain, and substrate, while the gate was powered up to 16 V and gate leakage was measured. Bad lots are displayed in red. While lot 6 was identified as bad after the commonality study, it initially was comparable to good lots in that it had very few failures (apart from the marginal bimodality of DR3 failures), demonstrating the complexity of troubleshooting in a complex fabrication process in which one dubious data point can confuse or lead investigators astray. Since plasma charging was no longer a primary concern, given that antenna ratios were well within design specifications and were similar from driver to driver, the commonality study began to concentrate on front-end process steps.

In the next phase of the study, several lots with marginal failures were excluded, resulting in the identification of the first metal etch step and tool as the primary causes of the DR3 GOX leakage failure—a significant finding, considering that the PBC4 process involves more than 100 tools and more than 300 steps and substeps. The functional data clearly supported the theory that the metal etch step was to blame—all lots exhibiting the bimodality had been processed in metal etcher B, a dual-chamber tool, while the clean lots had all been processed in metal etcher A, a single-chamber tool. Although both chambers in etcher B used the same metal-1 etch recipe, operational differences between them were causing the DR3 driver to exhibit different failure levels.

Figure 7: DR3 failures from lot 10, half of which was run in metal etcher A and half in metal etcher B. Much higher failure rates were found on wafers from the latter etcher than the former.

After the first metal etch step and toolset were identified as possible culprits, lot 10 was split in half and processed through the fab. Half of the lot was processed in metal etcher A, while the other half was processed in metal etcher B. As illustrated in Figure 7, much higher DR3 GOX leakage failures were observed on wafers run in the latter tool than in the former.

Implementing and Verifying a Solution

Magnetic fields are used in the etch recipe to increase plasma density, promoting a higher etch rate and improved etch uniformity. According to the published literature, issues with the magnetic fields in etchers can cause GOX degradation.³ This finding was confirmed by a PolarFab study involving plasma charging on high-antenna-ratio MOS devices, which had demonstrated that the higher the magnetic field in metal etch recipes, the higher the damage to the GOX. While a reevaluation of the antenna-ratio specification limits indicated that the metal-1 antenna ratio on the DR3 device was well within specification limits, problems with the magnetic field were discovered.

Parameter Old Recipe (Main Etch) Old Recipe (TiN Etch) New Recipe (Main Etch) New Recipe (TiN Etch) Cl2 (std cm3/min) 25 15 25 10 BCl3 (std cm3/min) 30 60 60 30 CF4 (std cm3/min) 5 0 10 10 N2 (std cm3/min) 25 20 20 20 Pressure (mTorr) 200 250 250 250 RF power (W) 700 650 700 700 Magnetic field (G) 90 60 45 0

Table I: New and old recipes used for main and titanium nitride liner etch on metal etcher B.

To investigate that finding, a "rifle-shot"-type experiment was designed in which metal etcher B ran half of lot 11 using the old recipe and half using a new recipe with a lower magnetic field. The recipes used for main and titanium nitride liner etch are provided in Table I. Gas flow and pressure in the new recipe were then changed slightly to improve such etch parameters as uniformity, etch rate, and etch bias. Test wafers used to optimize the recipe showed no evidence of DR3 GOX leakage, as demonstrated in Figure 8.

Figure 8: Yield results for lot 11 splits run on etcher B with old and new recipes, and on etcher A. No DR3 GOX leakage issues were seen with the new metal-1 etch recipe.

After the new etch recipe in metal etcher B was qualified using parametric and functional tests, it was approved for use in the PBC4 manufacturing process. Since PBC4 had not been in production when the new recipe was made available, the use of the recipe was authorized based only on the parametric and functional tests with in-line characterization. Figure 9 presents sample wafer maps generated after the DR3 gate leakage issue had been resolved. These maps represent the first stage of the qualification procedure; after additional minor process improvements were made, defect densities well below 1/cm² were achieved.

Figure 9: Wafer maps showing the results of the new etch recipe.

A qualification lot was processed through the fab with the new etch recipe and submitted for reliability testing. Table II describes the reliability testing performed on all technology qualification vehicles. This test met or exceeded published Joint Electronic Device Engineering Council (JEDEC) standards. After the new etch recipe had been qualified, many PACMAN4X lots were processed without GOX leakage problems. Six to eight months had passed between the discovery of the problem and its solution. The DR3 GOX leakage issue was remedied in a timely manner, so that the customer's schedule was not severely affected.

Test Conditions Read Points Life test Dynamic excitation at minimum 125°C temperature 168, 504, 1008 hour Temperature cycle –65° to 150°C, air to air 200, 500, 1000 cycles 85/85 Static bias at minimum power dissipation, 85°C/85% RH 168, 504, 1008 hour High-temperature storage 150°C 168, 504, 1008 hour Thermal shock –65° to 150°C, liquid to liquid 100, 300, 500 cycles Autoclave 30 psia, 121°C/100% RH 168 hour

Table II: Reliability testing parameters used for all technology qualification vehicles.

Conclusion

The ability to quickly identify and resolve problems that arise during the qualification phase is critical, especially given increasingly short design/development cycles and time-to-market trends. Process or design issues must be identified, analyzed, and solved rapidly to ensure success, especially in competitive and dynamic markets. In semiconductor manufacturing, the technology transfer and qualification step is crucial because it tends to uncover deficiencies that may require anything from a simple process change to a serious redesign. DR3 GOX leakage, the main issue encountered during PBC4 transfer and qualification, was a problem of moderate complexity.

Once a process fix has been identified and implemented, line monitoring becomes significant to ensure that the same problem does not resurface. In the case of PACMAN4X, the technology qualification vehicle is periodically processed and tested. To date, no chronic GOX-related issues have reappeared on PBC4.

At any given time, not all data are available for analysis. Therefore, the situation must be evaluated constantly as more data become available. Since the failure mechanism behind the DR3 GOX leakage was not further investigated, it is not clear which portion of the recipe failed. However, in a production environment, undertaking that type of investigation would have a purely academic character, detracting from the mission of achieving process qualification and meeting customers' time-to-market schedules.

Acknowledgments

The authors would like to thank PolarFab's operations, engineering, and quality departments for providing the parametric and failure analysis data to support this work. They are also indebted to the technology-transfer and technology-qualification groups for helpful technical discussions. In addition, they would like to thank Brent Sittlow for providing the etch recipes, Robert Fann for supporting graphics, and Robert Feldman, Jim Quiggle, and Steve Kosier for a critical review of the manuscript.

References

1. S Gupta et al., "Improved Latch-Up Immunity in Junction-Isolated Smart Power ICs with Unbiased Guard Ring," IEEE Electron Device Letters 22, no. 12 (2001): 600–602.

2. S Gupta et al., "Unbiased Guard Ring for Latchup-Resistant, Junction-Isolated Smart-Power ICs," in Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (Piscataway, NJ: IEEE, 2001), 188–191.

3. M Sekine et al., "Gate Oxide Breakdown Phenomena in Magnetron Plasma," Japanese Journal of Applied Physics, 34, part 1, no. 11 (1995): 6268–6273.

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Venuka K. Jayatilaka is a principal technology-transfer engineer at PolarFab (Bloomington, MN). Since joining the company in 2001, he has been responsible for the transfer of analog, mixed-signal technologies from R&D to volume production and has participated in the conversion of the 0.5-µm PBC4 process from 6- to 8-in.-wafer manufacturing. From 1996 to 2001, he worked as a technology development engineer at Cypress Semiconductor, where he developed 0.5–0.16-µm digital CMOS process technologies. Jayatilaka has three patents pending in the area of semiconductor processing. He received a BS in 1994 from the University of Texas in Austin and an MS in 1995 from the University of Wisconsin in Madison, both in electrical engineering. He is pursuing an MBA at the University of Minnesota in Minneapolis. (Jayatilaka can be reached at 952/876-3471 or jayatilakav@polarfab.com.)

Phillip B. Espinasse is a product marketing engineer at PolarFab. Since joining the company in 1999, he has held positions in process development and competitive analysis engineering. From 2000 to 2001, he also worked as an editorial consultant for VerticalNet, covering breakthroughs in photonics and fiber optics technologies. In 2000, he became an editor for SPIE's OE Magazine. Espinasse has authored more than 80 magazine and on-line technical publications dealing with optoelectronic-, photonic-, and semiconductor-related technologies, and has one patent pending. He received a BS in 1996 from Northwestern University (Evanston, IL) and an MS in 1999 from Iowa State University (Ames), both in electrical engineering. He is pursuing an MBA at the University of St. Thomas in Minneapolis. (Espinasse can be reached at 952/876-3183 or espinassep@polarfab.com.)