'Round The Circuit

Infineon chip finds faults

A new test chip developed by Infineon and Regensburg University of Applied Science quickly detects via faults during the manufacturing process, helping to increase productivity and decrease production costs. The device, rooted in an innovative circuit concept developed by university researchers, was produced and deployed at the German chipmaker's Regensburg site.

Based on a 0.35-µm CMOS process and fabricated on 200-mm wafers, the chip has a memorylike configuration and consists of an array of test structures with a smart, universal addressing circuit. The test device has more than 1.2 million transistors on a die area of 6 square millimeters. The company says that each via can be addressed individually, while its electrical resistance and voltage drop at the via can be measured precisely. Since the addressing function helps achieve such precise fault location, this allows the test instrument to detect the slightest process changes within the via sector of a device.

The test chip will first be used at its Regensburg fab and then rolled out to other production facilities, according to Infineon. The chipmaker and its university partner are continuing to develop the concept, hoping to deploy it in the future to other process steps to enable better circuit reliability and improved productivity.

EUVL on track, experts say

Extreme ultraviolet lithography may be well on its way to commercialization, but several daunting technical challenges must be addressed for the technology to stay on track. That was one of the key messages delivered to more than 350 lithographers gathered for the second International EUVL Symposium, held September 30 through October 2 in Antwerp, Belgium. Technical and regional progress reports were presented by experts from Japan, Europe, and the United States.

At the end of the event, the symposium's steering group identified six critical issues facing the industry over the next few years:

• Source output power and lifetime, including condenser optics lifetime.

• Availability of defect-free masks.

• Reticle protection during storage, handling, and use.

• Projection and illuminator optics lifetime.

• Resist resolution, sensitivity, and linewidth reduction.

• Optics quality for the 32-nm node.

Remarking on the state of EUVL development, Paolo Gargini, Intel's director of technology strategy, noted that "good progress has been made on all technology fronts. Commercialization in 2009 remains the main goal for all the EUV community." Although he recognized "a strong drive for developing EUV technology," symposium general chairman Rob Hartman of ASML said he "would like to see more firm commercial commitments from semiconductor companies."

KLA-Tencor nabs award

Citing the company for establishing best practices in manufacturing and supplier management through the implementation of its eQuality program, the Manufacturing Enterprise Solutions Association International (MESA) has awarded KLA-Tencor its Manufacturing Excellence Award. The prize, inaugurated this year, honors manufacturers that have achieved success in one of three categories: customer intimacy, product leadership, and operational excellence. KLA-Tencor received the award in the third category.

"We were extremely impressed with KLA-Tencor's ability to monitor, control, and optimize process and first-time product quality, synchronize manufacturing with other business processes, and increase utilization of production assets across the organization," remarked Julie Fraser, a principal of Industry Directions and MESA awards judge.

Commenting on eQuality, program manager John Moore described it as "a corporatewide system that tracks process and materials quality throughout the life cycle of every product we manufacture. By implementing this program, KLA-Tencor has achieved a return on investment of more than 200% and improved its gross margin by more than 2% through major improvements in installation time, cycle time, and overall quality."

In-house training offered

Semiconductor Services has created a one-day, in-house training course to help semiconductor manufacturing sector personnel better understand the production process. "CMOS—Recipe for Chipmaking Success" describes the stages of CMOS transistor fabrication, including technologies such as shallow-trench isolation, dual-damascene, and low- and high-k dielectrics. The course explains the major process steps in simple terms, using two- and three-dimensional graphics to help illustrate transistor building. The basics of the semiconductor business are also covered in the class.

"The CMOS integration course is designed to provide participants a working knowledge of IC fabrication so that they can perform their job functions more properly," according to Michael Haynes, the course's principal developer. Stanford consortium SemiZone also offers a Web-based version of the course. Demystifying IC Fabrication, a book based on the class, is scheduled for spring 2004 publication by Elsevier Science and Technology Books. For more information, visit www.semiconductorservices.com.