Defect/Yield Analysis and Metrology

Reducing gate-level electrical defectivity rapidly using voltage-contrast test structures

Oliver D. Patterson, Brian D. Crevasse, Keiko K. Harris,
Benu B. Patel, and George W. Cochran, Agere Systems

The gate level is generally one of the three largest sources of random yield loss, or yield-limiting defect density (D₀), in IC technologies because gate-level dimensions tend to be the smallest of all dimensions in order to maximize transistor density. At that level, yield loss occurs as a result of shorting from poly to poly or from poly to a contact. (Although amorphous silicon or some other material may be used to fabricate the gate and the poly may be topped off with a metal such as tungsten silicide (WSi), this article will refer to the gate material as polysilicon, or poly.)

The detection of defects that affect the gate and other levels becomes more difficult with each new technology generation. Each time critical dimensions shrink, a group of smaller defects becomes critical. These smaller defects are harder to detect. Equipment suppliers have addressed this trend by developing increasingly sophisticated optical and laser-based tools offering some relief. Several suppliers have also developed scanning electron microscopy (SEM) systems that are appropriate for inspecting large areas.

In addition to offering much greater resolution than other types of inspection tools, SEMs benefit from a phenomenon commonly referred to as voltage contrast.¹ Under certain conditions, grounded structures emit far more electrons than do floating structures. This phenomenon is very useful for detecting yield-limiting defects.^2,3 Despite these advantages, however, inspection SEM technology is slow. For example, scanning an entire 200-mm wafer can take nearly a day.

To address this issue, the µLoop electrical defect monitoring system was introduced by KLA-Tencor (San Jose).^4–6 This system uses an inspection SEM and special test structures to detect all killer defects. Using a concept known as area acceleration, the system inspects a small fraction (e.g., one-fiftieth) of the total area of the test structure. This method has proven effective at detecting opens and shorts in the back end that affect both metal runners and vias. Since the tool detects such killer defects using voltage contrast, it automatically filters out nonkiller defects. After defect detection, SEM review of all the defects found is performed to fully characterize the defects. The information gained from the review step is valuable for eliminating the defects types efficiently. Because inspection is conducted in-line, defect reduction experiments can be completed much more quickly than with traditional techniques.

Until recently, the monitoring system was not usable for gate-level inspection because the system's test structures require a ground path. However, in most, if not all, IC technologies, poly is isolated from ground by a gate oxide, and a window from the poly to the substrate is not an option. Although poly may be grounded using metal 1, metal 1 processing occurs too late in the manufacturing sequence to permit voltage-contrast inspection of the gate level.

This article explains how engineers at Agere Systems' wafer fab in Orlando, FL, were able to overcome this limitation by creating gate-level voltage-contrast test structures that can be used with the monitoring system, enabling them to extend the system's benefits to gate-level inspection of several technologies. The tests reflected in this article were performed on one such technology. By reviewing those tests, a method for utilizing the test structures was developed.

Experimental Procedure

Voltage-Contrast Test Structure for Detection of Shorts. A variety of voltage-contrast test structures, which test different aspects of process integrity, can be used with the monitoring system. The comb test structure, illustrated in Figure 1, is one such structure.⁴ The top comb is grounded, while the floating tines of a second comb are interleaved with the tines of the grounded comb. Since the second comb does not have a back, its tines are isolated from one another. Under voltage-contrast conditions, the tines of the grounded comb normally appear much brighter than the floating tines in SEM images.

Figure 1: Basic comb voltage-current test structure. The top comb is grounded.

Using this structure, both opensand shorts can be detected. If a conductive defect connects a floating tine to the grounded comb, the tine appears bright regardless of where it is scanned. If an open affects one of the tines of the grounded comb, the remainder of that tine appears dark. By inspecting the ends of the tines, these failures can be detected. A second inspection involving the full length of each defective tine is then used to find the actual defects. The length of the tines determines the amount of area acceleration that must be considered. A single inspection swath may be as narrow as 50 µm. For tines 2.5 mm long, the area acceleration is 50. In other words, only one-fiftieth of the comb area must be inspected.

Short-Loop Process Flow for Grounded Gate-Level Combs. For the monitoring system's test structures to work, a path from one segment of the test structure to ground (the substrate) is necessary. However, the lack of a suitable ground path deterred the development of gate-level test structures.

Consequently, a special process module was developed to enable the fabrication of grounded gate-level test structures. These structures are fabricated on short-loop test wafers and make use of the contact and metal 1 masks that are used to make metal 1 voltage-contrast combs. Although the pitch of these combs is greater than nominal for the gate-level module, it is close enough to allow the module to be debugged.

The masks used for these short-loop wafers came from Agere's full-flow test vehicle, which contains memory test chips, D₀ test structures, parametric test structures, and voltage-contrast (µLoop) test structures. The D₀ test structures are tested at probe and include combs to measure gate-level D₀. The monitoring system's test structures used to measure gate-level D₀ in-line cover 14 cm² of each wafer.

The process flow for this module is listed in Table I. First, a thin, 2000-Å oxide layer is deposited. Then windows to the substrate, referred to as window 0s, are formed. This layer is patterned using the contact mask. A very isotropic etch is used, since these windows cannot be filled with tungsten, which can contaminate the poly furnace. The sloped side walls offer the poly the best chance of contacting the substrate. The thickness of the oxide was selected using a design of experiment (DOE). If the oxide is too thick, the poly will not contact the substrate. If the oxide is too thin, alignment of the gate-level mask to the window mask is not possible.

The next step is poly deposition. The short-loop process flow duplicates the process flow for product lots from gate stack deposition onward, with the exception that gate oxide deposition is skipped because the poly must contact the substrate electrically. In Table I, inspection steps appear to the right of the process step they follow. Only a subset of these inspection steps was used for each lot. Lots subjected to this process flow are referred to as gate-level voltage-contrast zone testers.

Inspection Equipment. A KLA-Tencor eS20XP inspection SEM operating at 500 eV was used to perform µLoop inspections. High-resolution images were collected and composition analysis was performed using a review SEM. Wafers were inspected using KLA-Tencor's AIT2 defect inspection system with a 7-µm spot size.

Experimental Results

A set of 10 gate-level voltage-contrast zone tester lots were run over a period of nine months in an effort to reduce gate-level D₀. In order to maximize process efficiency, multiple lots were run together through the gate activation step. For example, lots 2 and 3 were run together, lots 4 and 5 were run together, lots 6, 7, and 9 were run together, and lots 8 and 10 were run together. A summary of the lots is presented in Table II. The experimental sequence and subsequent test results are discussed in this section.

The primary purpose of running lot 1 was to establish the test structure process flow. The DOE to determine proper oxide thickness was also explored with this lot. Lot 1 was expected to produce a yield-loss Pareto matching conventional wisdom at the time. Prior to running this lot, the widespread opinion based on in-line inspection data was that micromasking defects caused by particles from the etch process were the dominant defect type affecting the gate-level module. Surprisingly, the results from the lot 1 test did not confirm this assumption.

Figure 2: Two wafers from lot 1 with high defect counts have a strong top-left signature. (The defects are represented by black dots, and the boxes indicate where images were taken.)

Two of the six wafers from lot 1 had a strong top-left spatial defect signature, as shown in Figure 2. As illustrated in Figure 3, the remaining wafers were relatively clean. This spatial signature was caused by small round extras, which were consistently about 0.2 µm in diameter. These defects, illustrated in Figure 4, were not a result of etch flakes, which are irregularly shaped. It was apparent that they were generated some time after WSi deposition, since they included the full stack. Most likely they were from the clean 3 or gate lithography steps, which involve liquids and are likely to produce perfectly round defects. The defect Pareto in Figure 5 shows that very few other defect types affected lot 1.

Figure 3: Breakdown by wafer indicates that two of six wafers from lot 1 had relatively high defect densities. The defects were predominantly small round extras.

The next two experiments confirmed that the etch process did not contribute significantly to defectivity, freeing the gate etch engineers from D₀ reduction efforts and allowing them to focus on other aspects of the etch process.

Both lots 2 and 3 returned almost exactly the same results as lot 1: two or three wafers had small round extras concentrated in the top left of the wafer. Wafer maps for the affected wafers are presented in Figures 6 and 7. This signature was also found on three or four full-flow test-wafer lots run during this same period. Composite maps for several such lots are shown in Figure 8.

Figure 5: Defect Pareto for lot 1 showing that the killer defects were predominantly small round extras.

Lots 4 and 5 were designed to isolate the source of the small round extras. Both were partitioned using defect inspections E, F, G, and H and utilized a split experiment at the clean 3 step, which was deemed the most likely source of the defects. In that experiment, half of the wafers were run on the process of record (POR) tool, while the other half were run on a different tool from a different manufacturer using an alternate process. The hardmask deposition step of lot 4 was also split between wafers that were run on the POR tool and those that were run on an alternative tool using different timing. The results from such split experiments are very conclusive if the defect type appears exclusively on the wafers from one group.

Figure 7: Wafer maps (top) and SEM images (bottom) of defects from the two affected wafers in lot 3.

The most important finding from the experiments involving lots 4 and 5 was the lack of small round extras. No more than a few odd such defects were observed on any subsequent gate-level voltage-contrast zone tester lot. Perhaps the cause of this defect mechanism was eliminated during routine maintenance that occurred between the processing of lots 3 and 4. These maintenance activities may have been a little more thorough than normal because of the ongoing high-profile investigation into the source of the small round extras.

For lots 4 and 5, D₀s of 0.44 defects/cm² and 0.6 defects/cm², respectively, were captured. Stack defects, examples of which are shown in Figure 9, were the primary type detected. These spatially random defects were discovered during defect inspection E, indicating that they appeared before the clean 3 step. Not surprisingly, given the lack of small round extras in lots 4 and 5, no significant differences were observed between the splits for all the experiments. While lots 1, 2, and 3 also had stack defects, there were far fewer of them than of the small round extras.

Figure 8: Composite wafer maps from two full-flow test-wafer lots run during the same period as lots 1, 2, and 3. The numbers correspond to the number of bad poly combs at each location on all wafers across the entire lot. The maps indicate a top-left signature.

For lot 6, an additional inspection step, defect inspection C, was added before the pre-WSi HF dip step. Because of the possibility that small round extras might affect this lot, defect inspections E, F, G, and H were also included. In an attempt to isolate the source of the stack defects, the pre-WSi HF dip step was split between wafers run on the POR tool set and wafers run on an alternate tool set. Inspection data from recent product lots indicated that this step was possibly generating defects.

The D₀ of lot 6 was only 0.31 defects/cm². Stack defects were the primary defect type found, although a small number of partial extras that may have come from the etch chamber and some missing-pattern defects were also present. A Pareto chart containing these results is presented in Figure 10, and images of partial extras are shown in Figure 11. Partition results of killer stack, partial extra, and missing-pattern defects, shown in Figure 12, indicate that stack defects were introduced before the pre-WSi HF dip, while partial extras were either introduced after gate lithography or are not detectable using the defect inspection tool. Lot 6 was the only gate-level voltage-contrast zone tester lot affected by partial extras.

Figure 10: Pareto chart for lot 6. Stack defects were prevalent, while small round extras were no longer present.

Because of the changing nature of the yield loss affecting the gate module, lot 7 was run without any experiments to provide quick, additional data on the composition of the gate-level yield-loss Pareto. The D₀ for this lot was 0.15 defects/cm². Most of the defects were stack defects. Again, no small round extras were present. Lot 7 was the first lot run with the megasonic cleaning step before WSi deposition.

Because small round extras were not present in several of the later lots, experiments on lot 8 focused completely on discovering stack defects, for which defect inspections A, B, C, and G were performed. A pre-poly-deposition inspection step was not included because lot 8 had already undergone poly deposition.

Figure 12: Partition results for lot 6 indicating killer defect counts at various inspection steps for stack, partial extra, and missing-pattern defects.

Lot 8 also contained a three-factor, two-level split. Half of the wafers were subjected to a megasonic clean and half were not. Half of the wafers were subjected to a pre-WSi HF dip and half were not. And half of the wafers went through the gate activation step on the POR tool and half went through it on an alternate tool. There was no statistical difference between the split lots. At 0.06 defects/cm², the D₀ was extremely low, indicating that the defects that had prompted the engineers to perform the megasonic clean and pre-WSi HF dip steps may not have been present after all. Defect inspections on all the split lots indicated small, equal numbers of killer defects.

Like lot 7, lot 9 was run without experiments to provide additional data on the composition of the yield-loss Pareto. Its D₀ was 0.55 defects/cm², most of which were stack defects. Lot 10 was split between wafers that were run with a megasonic clean step and those that were run without it. The D₀ for this lot was 0.05 defects/cm².

Lot 9 was processed together with lots 6 and 7 through the gate activation step, and all three had very low D₀s. They went through gate activation in July. In contrast, lots 8 and 10 went through gate activation in November. In the interim, the poly furnace had been improved. In addition, two process changes had been introduced at the gate activation step, one of which was believed to have caused the significant drop in D₀.

Figure 13: Box plot comparing defect counts for wafers run with or without a megasonic clean.

Figure 13 shows killer-defect results for lot 10 wafers that went through the megasonic clean step versus those that did not. Even at low defectivity levels, the megasonic clean step appeared to remove particles that caused shorts. Similarly, the wafers in lot 8 that underwent the megasonic clean step had fewer defects than those that did not, although that difference was not strong enough to be considered significant.

Conclusion

The experiments using gate-level voltage-contrast zone tester wafers never isolated a process step sufficiently to motivate a tool clean or process upgrade. However, the experiments did help to focus engineers' attention on the largest defectivity problems. The experiments also quickly indicated which steps did not generate defects, allowing process engineers to concentrate on other activities. The gate-level voltage-contrast zone tester methodology allowed engineers to conduct many defectivity experiments extremely quickly because of the prompt feedback provided by the electrical defect monitoring system. Moreover, this methodology has nearly perfect sensitivity to yield-limiting defects: nearly 100% of the killer defects in the experiments discussed in this article were detected, while nonkiller defects were ignored.

Figure 14: Gate-level D0 trend chart over the period of the investigation. The average D0 dropped 62%.

Most important, during the nine-month testing period, gate-level D₀ dropped 62%. For a typical 0.2-cm² chip, the yield gain resulting from this decreased defectivity was 3%, while for a typical 1-cm² chip, the yield gain was 8%. These data are based on a critical-area-analysis yield model. Figure 14 shows the gate-level D₀ trend over this period derived from an analysis of full-flow test wafers. Some of the yield improvement can be attributed to these experiments.

The electrical defect monitoring methodology should be used in conjunction with other techniques, including partition and split experiments. In addition to driving baseline improvement, the gate-level voltage-contrast zone tester can be a useful tool for monitoring the health of a manufacturing line.

Acknowledgments

This article is based on a paper presented at the Advanced Semiconductor Manufacturing Conference, held March 31–April 1, 2003, in Munich.

The authors gratefully acknowledge the contributions of David Hwang, Glen Abeln, Steve Meisner, Steve Neston, and Mario Pita for their help in developing the process module discussed in this article. They also thank Brian Harding, Greg Head, and Bob Dyas for their process-specific support. In addition, the authors would like to acknowledge Jose Chacon, Alan Olds, and William Bevers for their help in developing and executing the split experiments discussed above. They also thank Fred Weck for his help with the inspection database and computer interfaces, and Bill Russell for his many helpful suggestions about the organization of the article. Finally, they wish to thank Kurt Weiner, Todd Henry, Richard Wu, Guarav Verma, Akella Satya, Isabelle Lewis, and Glen Liddell of KLA-Tencor for sharing the µLoop concept early on, for setting up the system at Agere, and for the productive years spent in jointly developing the first commercial system.

References

1. A Nishikawa et al., "An Application of Passive Voltage Contrast (PVC) to Failure Analysis of CMOS LSI Using Secondary Electron Collection," in Proceedings of 1999 International Symposium for Testing and Failure Analysis (Materials Park, OH: ASM International, 1999), 239–243.

2. OD Patterson et al., "Real Time Fault Site Isolation of Front-End Defects in ULSI-ESRAM Utilizing In-Line Passive Voltage Contrast Analysis," in Proceedings of the 28th International Symposium for Testing and Failure Analysis (Materials Park, OH: ASM International, 2002), 591–599.

3. V Liang, H Sur, and S Bothra, "Passive Voltage Contrast Technique for Rapid In-Line Characterization and Failure Isolation During Development of Deep-Submicron ASIC CMOS Technology," in Proceedings of the 24th International Symposium for Testing and Failure Analysis (Materials Park, OH: ASM International, 1998), 221–225.

4. K Weiner et al., "Defect Management for 300 mm and 130 nm Technologies, Part 3: Another Day, Another Yield Learning Cycle," Yield Management Solutions Magazine 4, no. 1 (2002): 14–27.

5. J Shaw et al., "Rapid Interconnect Development Using an Area Accelerated Electron Beam Inspection Methodology," in Proceedings of the International Interconnect Technology Conference (Piscataway, NJ: IEEE, 2002), 33–38.

6. RL Guldi et al., "Characterization of Copper Voids in Dual Damascene Processes," in Proceedings of the Advanced Semiconductor Manufacturing Conference (Piscataway, NJ: IEEE, 2002), 351–355.

Oliver D. Patterson, PhD, is a member of the technical staff in the defect reduction engineering group at Agere Systems (Orlando, FL). He develops and implements yield improvement tools and methodologies. He also plays a key role in yield modeling for the company worldwide. His other responsibilities include front-end lot analysis, process analyst training, and engineering wafer starts coordination. Previously he worked for the U.S. Air Force materials laboratory, where he developed control strategies for advanced materials processes. Patterson was Agere's representative on the International Sematech yield management tools program advisory group and yield council until July 2003 and is a member of the technical committee for ASMC. He received an SB from the Massachusetts Institute of Technology (Cambridge) in 1985, an MS from the University of Wisconsin (Madison) in 1987, and a PhD from the University of Michigan (Ann Arbor) in 1998, all in electrical engineering. (Patterson can be reached at 407/371-3879 or odp@agere.com.)

Brian D. Crevasse worked at Agere Systems in the fields of yield improvement (SEM inspection/review) and process engineering (plasma etch). Currently he is a manufacturing process engineer in the direct radiography division at Hologic (Bedford, MA). Before working at Agere, he served as a field process engineer in the plasma etch area at Lam Research and as a materials and process engineer at Honeywell Avionics. He received a BS in chemical engineering from Georgia Institute of Technology (Atlanta) in 1985. (Crevasse can be reached at 302/631-2787 or bcrevasse@hologic.com.)

Keiko K. Harris is the tool owner and principal engineer of the AIT-I and AIT-II in-line inspection tools at Agere Systems, where she conducts experiments to characterize defects, identify defect sources and mechanisms, and reduce defectivity. She has been with Lucent Technologies and Agere since 1998 in the ion implant and defect reduction groups. She received BS and MS degrees in materials science and engineering from the University of Florida in Gainesville. (Harris can be reached at 407/859-7503 or keikokharris@netscape.net.)

Benu B. Patel is a member of the technical staff at Agere Systems. She has worked for AT&T, Lucent Technologies, and Agere Systems since 1994. At Agere she has had assignments as a manufacturing technologist for CMOS technologies, as a development engineer for 0.25-µm SiGe technology, and as a defect-reduction engineer specializing in front-end processing. Previously, she was a manufacturing technologist at the company's linear bipolar fab in Reading, PA. She received an MS in electrical engineering from Georgia Institute of Technology in 1993. (Patel may be reached at 407/371-6281 or at bbp@agere.com.)

George W. Cochran is the tool owner and principal engineer of the in-line optical and SEM review tools, including automatic defect classification, at Agere Systems. He is also a member of the front-end defect reduction team that identifies defects in that area. Cochran has worked for AT&T, Lucent Technologies, and Agere Systems since 1985. He has had assignments in secondary ion mass spectrometry, product engineering, and defect reduction. He received a BS in chemistry from Indiana University in Bloomington and an MBA from Nova University in Ft. Lauderdale, FL. (Cochran can be reached at 407/371-6925 or gcochran@agere.com.)