New Materials Integration

Fabricating and inspecting ultrathin silicon-on-insulator wafers

Christophe Maleville, Soitec; and Lisa Cheung and Dieter Mueller; KLA-Tencor

Initially used for niche applications such as hardened devices, silicon-on-insulator (SOI) technology has evolved over the last 25 years. Following IBM's example in the late 1990s, leading IC suppliers have come to realize that they can achieve greater device speed and less power consumption using SOI wafers than with conventional silicon wafers.¹ SOI material has become a substrate of choice for advanced microprocessor applications and is being used increasingly in high-volume production.

Materials in general are taking center stage in the performance race, since it appears that scaling alone is not enough to keep pace with Moore's Law. In the race for faster microprocessors, fully depleted designs are being targeted for sub-90-nm devices, creating a need for ultrathin SOI material. When operating in fully depleted mode, transistor threshold voltage is directly linked to silicon thickness. As a result, thickness uniformity is becoming a critical parameter to guarantee threshold voltage (Vt) control. According to The International Technology Roadmap for Semiconductors (ITRS) guidelines, 20-nm silicon layers with ±5%, 6σ uniformity will be needed in high-volume manufacturing in the 2004 time frame.² That requirement has led to ±10-Å thickness accuracy on 300-mm wafers. The manufacturability of ultrathin SOI material is key to achieving that specification in silicon-based processes.

This article discusses the Smart Cut method used by Soitec (Bernin, France) for high-volume manufacturing of Unibond SOI wafers.³ Volume production of these SOI wafers demonstrates that high yields can be achieved by controlling splitting and bonding steps at production levels. Taking advantage of the flexibility of standard semiconductor equipment, the process has been successfully scaled up to 300 mm. The article also focuses on the need for metrology tools to attain high accuracy and sensitivity, emphasizing thickness monitoring and defectivity control. Finally, the article assesses surface nanotopography properties and new metrology techniques driven by lithography and CMP requirements.

High-Volume SOI Manufacturing

200-mm High-Volume Manufacturing Experience. Smart Cut technology is used at Soitec's Bernin I facility to produce 800,000 Unibond SOI wafers per year. That technology is based on thermal oxidation, ion implantation, wafer bonding, and atomic-level splitting. Its key feature, hydrogen implantation, weakens the silicon crystal at the desired depth, allowing a thin layer of silicon to be transferred and bonded on a base wafer.

Figure 1: Sum of>0.16-µm defects per wafer for more than 50,000 wafers grouped per production week. Results are from wafers with 1100-Å silicon film layer and 2000-Å BOX film layer. (Typical CZ and epitaxial wafer performance for the same defect threshold is provided for comparison.)

Unibond products in all diameters up to 200 mm and for applications ranging from thin to thick films have been qualified in production facilities. The chart in Figure 1 shows that more than 50,000 SOI wafers had <20 defects/wafer in the >0.16-µm size range, which outperformed the defectivity level of Czochralski (CZ) wafers and compared favorably with that of epitaxial wafers.

300-mm SOI Wafer Manufacturing. Several IC suppliers have qualified and ramped 300-mm fabs running advanced SOI applications. Using standard semiconductor process and metrology equipment, the Smart Cut technique was first extended to the manufacture of 300-mm wafers in 1997. Sample 300-mm wafers were fabricated in 2000, and a 300-mm pilot line was begun at the Bernin I facility in 2002. Just as 300-mm silicon wafer production rests on 200-mm technology, 300-mm SOI wafers are produced using an improved version of 200-mm production techniques. Moreover, nanotopography improvements at the 300-mm size have been particularly beneficial. From a manufacturing point of view, the 300-mm line, except for the use of front-opening unified pods (FOUPs) for all equipment and processing steps from incoming material handling to shipment, resembles the 200-mm line.

Table I compares 200- and 300-mm equipment and configurations. In the 300-mm production line, high-temperature anneal is performed using a boat specially designed to reduce wafer stress. Oxide uniformity on 300-mm wafers is typically the same as that on 200-mm wafers. For the implantation step, both the 200- and 300-mm lines use the same process equipment (including the hydrogen beam). Because 300-mm processing uses smaller batches than 200-mm processing (13 as opposed to 17) and 300-mm wafers have 30% more surface area than their 200-mm counterparts, implantation at 20 keV for new-generation products requires improved source and beam line configurations running on a 75-mA current. Under these conditions, it takes one hour to implant 13 300-mm wafers.

Because material handling is performed with FOUPs, a dry-in/dry-out polishing tool is used. Nevertheless, endpoint detection using in situ reflectivity monitoring lowers wafer-to-wafer mean-thickness variations.

Achieving Ultrathin SOI Films

Roadmap Targets. With fully depleted devices, threshold voltage is linked to silicon film thickness. In order to guarantee Vt stability over all produced devices, silicon film thickness must be strictly controlled, compelling manufacturers to achieve ±10-Å film-thickness accuracy on 300-mm wafers. It appears that such high uniformity (nano-uniformity) must be guaranteed at all spatial wavelengths down to the angstrom level.

SOI wafer manufacturing technology can be extended to very thin silicon and oxide films. For example, 500-Å silicon films are already running in production, while 200-Å films are in the advanced prototyping phase. Furthermore, the feasibility of producing bonded wafers consisting of a 100-Å silicon film and a 200-Å buried oxide (BOX) insulating film has been demonstrated. The roadmap in Table II addresses SOI film thickness and roughness targets for both 200- and 300-mm wafers at the 65-nm node and beyond.

Figure 2: 200-mm UT1 overall thickness uniformity chart for product with 550-Å silicon layer and 1450-Å BOX layer. For all sites on all wafers, thickness is within 550 ± 30 Å, 6σ.

UT1 Production Specifications. Production of the UT1 process generation is designed to achieve ±50-Å film thickness variation. Uniformity is calculated at 6σ (mean = ±3σ), assuming that 200-mm wafers are measured using more than 1700 points and 300-mm wafers are measured using 4000 points. By plotting minimum (–3σ) and maximum (+3σ) values for each wafer, overall uniformity is obtained for all wafers at all sites, as illustrated in Figure 2. Uniformity is typically driven by two parameters: wafer-to-wafer mean thickness variation and on-wafer sigma. For a typical 200-mm sample lot, wafer-to-wafer mean thickness is controlled at ±15 Å, while typical within-wafer thickness uniformity is approximately 4.5 Å.

Uniformity cannot be decoupled from surface roughness. UT1 wafers combine both parameters well. The atomic force microscope (AFM) images in Figure 3 demonstrate that for both 1 X 1 and 10 X10-µm scans, roughness is maintained at very good levels, especially when the roughness measurement is <2 Å root-mean-square (rms). At that level, interface roughness values are also low.

Figure 3: UT1 Surface-roughness measurement of (a) 1.5 Å for 1 X 1-µm AFM scan, and (b) 2.7 Å for 10 X 10-µm AFM scan.

Still in the ramp-up phase, the 300-mm UT1 process can achieve ±50-Å total uniformity on wafers with an edge exclusion up to 3 mm. All 300-mm characterization parameters—including defect density, roughness, hydrofluoric acid (HF) defect density, secco defects, metallic contamination, and electrical properties—are equivalent to their 200-mm counterparts.

Figure 4: Map of 200-mm as-split UT SOI structure. Minimum thickness = 561 Å, maximum thickness = 568 Å, mean thickness = 565 Å, and thickness range = 7 Å.

Next-Generation SOI Wafers. For Unibond performance to meet future ITRS targets, thinner and more-uniform films must be manufactured. Final uniformity is a result of oxidation, implantation, and polishing steps. In the new process generations listed in Table II, oxidation and implantation optimizations lead to very uniform as-split structures with ~1-Å uniformity (1σ). As illustrated in Figure 4, UT1, UT2, and XUT processes are based on such a highly uniform (7-Å-range) as-split SOI structure. Final thickness properties of wafers from these process generations will be achieved by implementing process steps to decrease surface roughness on the as-split structure.

Figure 5: TEM cross section of top silicon layer from a UT2 generation wafer with 500-Å silicon layer and 1500-Å BOX layer. The image shows very good silicon uniformity and a sharp silicon/BOX interface.

In the UT2 generation, implantation can be accomplished using low energy levels from 5 to 10 keV, producing films with top silicon thicknesses of 200 to 500 Å. The transmission electron microscope (TEM) cross-section in Figure 5 demonstrates that crystalline quality and interface sharpness are not degraded in such ultrathin films.

UT2 wafers exhibit standard deviations of <5 Å across all 300-mm wafers with a 3-mm edge exclusion. Combined with ±5-Å control of mean thickness value wafer to wafer, UT2 wafers have ±20-Å overall uniformity, as shown in Figure 6 for wafers with a 200-Å silicon film layer and a 1500-Å BOX film layer.

Improvements in splitting and finishing steps have lowered surface roughness to 1.0 Å rms for 1 X 1-µm scans and 3.5 Å rms for 10 X 10-µm scans. Figure 6 shows surface roughness on a 10 X 10-µm AFM scan.⁴ While the UT2 process achieves better thickness control at the wafer level than the UT1 process, it results in relaxed properties at the micron scale.

SOI roadmap projections require ±10-Å silicon layer uniformity for the 2005 time frame. That result has been achieved in initial tests of the XUT process generation on 200-mm wafers with a 700-Å silicon film layer and a 1000-Å BOX layer. In those tests, an 11-Å uniformity range (2-Å standard deviation) has been achieved. As shown in the wafer thickness map and chart in Figure 7, comparable performance has been attained on 300-mm wafers. For 300-mm XUT wafers with a silicon film thickness of 491 Å and a BOX film thickness of 1450 Å, a film thickness range of 12 Å has been achieved, enabling ±10-Å overall thickness control for the silicon layer on all wafers and all sites. That result has been accomplished using stringent control of wafer-to-wafer mean thickness and metrology optimized to achieve repeatability and accuracy at the angstrom level.

Ultrathin SOI Metrology

The aggressive targets for next-generation SOI substrates will rely on accurate metrology techniques. For applications 65 nm and below, advanced SOI structures must meet increasingly stringent metrology criteria. Geometry parameters such as thickness uniformity measurement, nanotopography and flatness monitoring, and defectivity monitoring represent difficult challenges.

Thickness Uniformity Measurement. Thickness is used as a generic term for several parameters and is to be assessed mainly depending on the uniformity scale in question. In metrology involving lateral scanning using AFM or TEM, uniformity control ranges from the micron to the wafer scale. In lithography applications, flatness and nanotopography are also key parameters on the z-axis.

Films are measured using ellipsometry or reflectometry techniques. For wafer-bonding-based SOI technologies, a BOX layer is grown and embedded in the structure. Then the silicon and oxide layers can be measured separately, allowing accurate monitoring using reflectometry. Multiple measurement results are shown in Figure 8 for two different products. In Figure 8a, the 500-Å film measurements have a mean variation of <1% (1σ = 2%), while in Figure 8b, the 215-Å product can also achieve the same good repeatability if the BOX thickness is fixed in the recipe. Using 6σ distribution (all wafers, all sites), the fixed BOX recipe is compatible with ±20-Å specifications, demonstrating excellent performance on bonded wafers.

When the BOX layer is generated in the silicon volume (as in the separation by implantation of oxygen [SIMOX] technique), surface and interface roughness monitoring requires the use of ellipsometry techniques to attain accurate layer measurements. Wafer-scale uniformity is generally achieved at the expense of a slight increase in micron-scale roughness. Whatever measurement technique is used, surface roughness degrades measurement accuracy, causing it to deviate from the tight thickness control required to monitor ultrathin layers.

The tests discussed in this article were performed on different product types with silicon thicknesses ranging from 100 to 500 Å and oxide thicknesses from 1000 to 1500 Å. Furthermore, six ellipsometers and one reflectometer from different suppliers were used. The diversity of products and tools led to measurement discrepancies. For all products processed on all tools, a ±20-Å thickness variation was obtained, highlighting the need to calibrate the monitoring equipment.

Nanotopography and Flatness Monitoring. Nanotopography and flatness monitoring are critical at different steps in the SOI process manufacturing flow. The nanotopography and flatness of incoming bulk wafers are key parameters because of their impact on final wafer properties and wafer bondability. Since the flatness properties of incoming 200- and 300-mm wafers undergo only minor changes during SOI processing, precise and comprehensive measurement capabilities are necessary to detect minute variations in topography on the final SOI wafer surface.

The work discussed in this article relied on the NP1 differential interferometer from KLA-Tencor (San Jose) for both silicon and SOI characterization. The instrument independently scans the front and back surfaces of the wafer, which is held vertically to avoid gravitational deformations. By combining wafer shape, edge roll-off, thickness or flatness, and nanotopography measurements in a single scan, the tool provides data that are necessary for nanotopography and wafer geometry monitoring in SOI manufacturing.

Figure 9: Thickness map of NP1 wafer with 26 X 33-mm sites and 1-mm edge exclusion. Typical site flatness is between 0.05 and 0.07 µm. Flatness degradation at the wafer edge is caused by SOI/bulk transition.

The tool can perform dual-side topography measurements with high sampling resolution at the wafer edge in a single measurement. Furthermore, oblique-angle illumination minimizes reflectivity- and roughness-induced artifacts, as depicted in the thickness map in Figure 9. Even during the SOI process flow, geometry parameters can be controlled on bulk and SOI wafers using similar recipes providing fast feedback on final characteristics.

At the 65-nm node, lithography and CMP requirements demand increasingly precise site flatness and nanotopography monitoring and control as early as the SOI substrate manufacturing stage. Lithography processes require site flatness, while dishing and erosion encountered during shallow-trench isolation polishing are linked to surface nanotopography.

Device yields on SOI wafers depend greatly on SOI-specific defects and on the wafers' edge exclusion. SOI wafers exhibit a non-SOI area because they cannot be bonded right up to the beveled edge. The width of the non-SOI area is linked to the roll-off properties of bonded wafers. Roll-off parameters are extracted from metrology data and illustrate how quickly the wafer surface decreases at the edge. Depending on wafer roll-off, the typical edge slope is in the 1–1.5-mm range, although some vendors have improved edge properties on 300-mm wafers so that the non-SOI area has been reduced to ~1 mm.

Nanotopography data are helping to close the gap between micron- and wafer-scale thickness measurements. Depending on the reference plane definition at the silicon/oxide interface, nanotopography can be linked to top-silicon thickness variations, thus providing uniformity information at the millimeter scale.

Defectivity Monitoring. According to the 2001 ITRS, it is critical to detect 65- and 45-nm defects in order to meet defect-monitoring requirements at the 90-nm node.¹ However, a variety of factors, including increasing instrument noise and noise from the wafer surface, hinder the measurement of small particles and other defects on bare wafer surfaces. Both instrument noise and wafer-surface noise affect the scattering light from the metrology process.

Detecting defects on SOI wafers using laser scattering inspection systems is complicated by the need to maintain the same low defect-size thresholds (65 and 45 nm) as in silicon wafer inspection. However, reflectivity changes during the inspection of some SOI wafers with surface properties equivalent to that of bulk silicon can prevent inspection equipment from detecting defects <100–200 nm.⁵ Reflectivity, in turn, depends on the thickness of the thin top silicon film and the buried oxide film as well as on the laser beam angle of incidence. In the case of SOI wafers, reflectivity and surface/interfacial roughness result in background scattering noise known as haze. The relationship between reflectivity and haze is illustrated in Figure 10.⁶

Figure 10: Chart demonstrating dependence of reflectivity on silicon film thickness on wafer with 1450-Å BOX film. Haze level is in inverse proportion to reflectivity, leading to high background levels on "dark wafers."

Wafer background haze can be lessened using appropriate recipes. The KLA-Tencor SP1^DLS inspection system with improved signal-to-noise detection based on increased laser power and improved signal analysis can be used to achieve low defect thresholds. Proper polarization and spatial filtering of scattering signals are also possible means to aid detection on SOI products.

Reflectivity also affects sizing accuracy on the wafer because it artificially changes the illumination level at the defect location. For a given particle size, two extreme reflectivity conditions can alter scattered-light intensity by two orders of magnitude. In order to evaluate the impact of reflectivity on sizing, 155-nm polystyrene latex spheres (PSLSs) were deposited, scanned, and sized on wafers showing the greatest reflectivity gap. Using only standard bare-silicon calibration curves, the sizing difference was determined to be 30%. For example, in the highest reflectivity case, 155-nm particles could be detected using a 200-nm threshold. Defects on shiny wafers (wafers with reflectivity higher than that of bulk silicon) appeared larger than those on less shiny (low-reflectivity) wafers.

To address the impact of reflectivity on sizing accuracy, well-calibrated SOI film curves can be used, since a particle signal depends on the silicon substrate thickness. However, while helping to improve sizing accuracy, dedicated calibration curves are time-consuming to use and applicable only on stable reflectivity domains. For example, the smallest PSLS size detectable on SOI wafers is ~80 nm for highly reflective wafers (R > 0.85).⁵ But defects smaller than 250 nm may not be detected on wafers with low reflectivity (R < 0.1) without the use of additional optical configurations.

Since wafer uniformity is not perfect, lasers can be employed to see reflectivity changes when scanning the wafer, generating dynamic threshold effects. The threshold can be decreased using the SP1^DLS tool's advanced optical configurations. With a UV laser, incoming light is absorbed before being reflected by wafer interfaces, eliminating further interference. Under these circumstances, SOI wafers behave like bulk substrates, and, with the highest sensitivity allowed by the UV laser, very aggressive roadmap targets can be met.

While using a UV laser, multiple recipes are needed to accommodate silicon thickness evolution during wafer processing. As film thickness decreases and laser absorption is reduced, the induced reflectivity of SOI structures approaches the extreme level of 0 or 1. However, wafer inspectability must be preserved, especially for low-reflectivity wafers with enhanced surface roughness. On XUT wafers, surface roughness is reduced for the full spatial frequency spectrum. Figure 11 shows 1 X 1-, 10 X 10-, and 40 X 40-µm AFM scans from XUT product with roughness of 1.2, 2.2, and 4.2 Å rms, respectively. At those roughness levels, low-threshold measurements can be performed even on "dark" wafers, such as the product with a 500-Å silicon layer and a 1450-Å BOX layer shown in Figure 8. And at those levels, 300-mm SOI wafers have a low defect density (<50 defects/wafer). These levels have been confirmed through HF revelation, which is performed to enlarge smaller defects to make them more visible. After HF revelation, the defect density on 300-mm SOI wafers is 0.05 defect/cm².

Conclusion

Soitec produces 200-mm SOI wafers in high-volume manufacturing that have achieved defectivity levels comparable to those of epitaxial wafers. Similar wafer quality has been attained in 300-mm manufacturing using roughly the same tool set and process configuration. New process strategies have improved layer uniformity so that products can meet IC supplier roadmap targets for the 90-nm node and below. The XUT product generation offers high uniformity (±10 Å) and is production-worthy at 200 and 300 mm.

In SOI wafer fabrication, metrology is crucial to achieve low surface roughness and nanotopography levels, enabling wafer inspectability at low thresholds. Nanotopography monitoring has been demonstrated to be the appropriate technique for assessing nanouniformity levels of SOI layers. Thickness measurement accuracy on ultrathin SOI films is still in need of improvement. Meanwhile, defectivity control at low threshold levels for advanced SOI structures is very challenging. The use of UV lasers enhances defect detection and eliminates reflectivity concerns.

References

1. SOI Newsroom [cited 10 September 2003]; available from Internet: www.soisolutions.com/news.html.

2. The International Technology Roadmap for Semiconductors (San Jose: Semiconductor Industry Association, 2001); available from Internet: http://public.itrs.net.

3. M Bruel, "Application of Hydrogen Ion Beams to Silicon on Insulator Material Technology," Nuclear Instruments and Methods in Physics Research B, 108, no. 3 (1996): 313–319.

4. C Maleville et al., "Unibond SOI Wafers for Ultra-Thin Films Applications," in Proceedings of the Silicon-on-Insulator Conference (SOI) (Piscataway, NJ: IEEE, 2001), 155–156.

5. C Maleville et al., "Laser Scattering Characterization of SOI Wafers: Real Threshold Assessment and Sizing Accuracy," in Proceedings of the Silicon-on-Insulator Conference (SOI) (Piscataway, NJ: IEEE, 2002), 194–195.

6. A Zeng et al., "Recipe Guidelines for the SP1^TBI, KLA-Tencor Surfscan SP1," Application note (San Jose: KLA-Tencor, 2000).

Christophe Maleville, PhD, is process engineering manager at Soitec (Bernin, France). Since 1993 he has been involved with the development of the Smart Cut process in collaboration with Commissariat à l'Energie Atomique/Laboratoire d'Electronique de Technologie d'Information (CEA/LETI) and has worked on its application to the manufacturing of SOI wafers. Currently he participates in new SOI process development and in transferring SOI technology to production. He has authored or coauthored more than 30 papers dealing with SOI manufacturing and metrology and holds approximately 15 patents in that area. He received a PhD in microelectronics from the Institut Polytechnique de Grenoble. (Maleville can be reached at +33 4 76927584 or christophe.maleville@soitec.fr.)

Lisa Cheung is the field marketing manager for the Surfscan Division of KLA-Tencor (San Jose). Since joining the company in 1998, she has worked in the areas of wafer inspection and yield improvement with the company's Surfscan SP1 line. Before joining the company, she was a sputter process engineer working on defect reduction at Seagate Technology. She received a BS in chemical engineering from the University of California, Berkeley. (Cheung can be reached at 408/875-7843 or lisa.cheung@kla-tencor.com.)

Dieter Mueller is a marketing manager for KLA-Tencor's wafer geometry products. Before joining KLA-Tencor in 1999, he held several management positions in product development and was cofounder and CTO of Nanopro, a German company specializing in the development of advanced interferometric technology for measuring semiconductor wafer shape and thickness. He received a degree in chemical engineering from Technikum Reutlingen, Germany. (Mueller can be reached at 408/875-4552 or dieter.mueller@kla-tencor.com.)