One approach employed by equipment suppliers is to provide both low-cost-of-entry R&D systems and ones that are more suitable for production. Processes must be transferable from the development phase to production with minimal additional process optimization efforts. While a manual load system and a set of processes intended for device feasibility, prototyping, or even low-volume manufacturing may be appropriate for the laboratory or small facility, a cassette-to-cassette system and an enhanced set of processes is more fitting when volume production and cost-of-ownership issues are posed. A combination of different equipment sets enables a smooth transition from innovation to commercialization.

This article discusses improvements in MEMS processes and hardware that have resulted in enhanced reproducibility and uptime, high throughput, and improved structure profiles and morphology. It focuses on high silicon-etch rates, smooth sidewall morphology, endpoint detection and its application to silicon-on-insulator (SOI) processes, and process control.

High Silicon-Etch-Rate Processing and Profile Control

Unfortunately, etch rate discussions among engineers and technicians often do not take place in the context of the device being fabricated, the needed throughput, or market demands. However, the equipment configuration needed in a given situation and the corresponding cost should be considered. For example, the silicon etch rates required in the laboratory are often much lower than those needed for production.

Silicon etch rate strongly correlates with free fluorine concentration. High fluorine radical values are obtained with high SF₆ flow rates and relatively large coupled power to dissociate the SF₆. Thus, fast etch rates are achieved most economically when pumping capability and power supplies are matched to the appropriate application.

Trench Dimension (µm) Etched Depth (µm) Etch Rate (µm/min) 2.5 15 8 30 40 12 100 100 18

Table I: Sample etching rates for features of various dimensions.

When high-rate etching is required either to achieve high throughputs or to avoid unendurable process times in the laboratory, it is important to maintain feature profiles without causing unnecessary mask undercut or roughness. Table I provides some examples of achievable etch rates and depths. Figure 1 shows a 30-µm trench feature with vertical sidewall profiles created at a rate of ~12 µm/min. Etch rates approaching 20 µm/min can be achieved with larger features, and even higher etch rates are possible when sidewall profile is not a primary consideration.

Figure 1: SEM image of a test structure feature 30 µm wide and 40 µm deep that has been etched at nearly 12 µm/min. It has maintained vertical sidewall profiles.

The extensive range of feature sizes and aspect ratios has made profile control a challenging issue. One way of controlling feature profile is to use a technique sometimes referred to as morphing.^1,2 With morphing, etch parameters are changed automatically and smoothly during processing. By adjusting process variables such as pressure, gas flows, and power during etching, the profile can be adjusted to compensate for changes in mass transfer of reagents and products as the features are etched. Figure 2 illustrates a process that has been morphed to provide a vertical structure.

Sidewall Morphology

Applications requiring extremely smooth sidewalls typically are used in fluid dynamics, such as micromixing chambers, or serve an optical function, such as photonic switches. Achieving the desired degree of smoothness on a vertical profile while maintaining an acceptable etch rate has proved challenging using traditional deep silicon-etch techniques.

Figure 2: Effects of profile control on a freestanding structure (a) without morphing, and (b) with morphing. The morphed structure avoids the taper seen in the unmorphed feature.

The Bosch process, which has generally been accepted for deep silicon etching, results in the formation of scallops on the sidewalls of etched structures. This manifestation of sidewall roughness is a direct consequence of alternating deposition and etch cycles. The timing of the steps in each cycle can be directly correlated to the etch rate and sidewall roughness. The roughness issue can be addressed by including additional gases in the process, such as oxygen or nitrogen, to encourage a more anisotropic etch behavior. Although this approach reduces roughness, it is difficult to control and lowers the etch rate.

Another method for decreasing sidewall roughness utilizes shorter etch cycles. The length of the etch cycle is primarily limited by the relatively slow response of mass-flow controllers (MFCs). Fast digital MFCs have improved the situation.³ Nevertheless, they still may be limited in their ability to stabilize gas flows or avoid a flow burst at the start of each cycle, either of which affects process reproducibility and stability. Reducing the initial gas surge by maintaining a minimal flow rate during the off cycle causes process gas flow overlap and has not been successful in producing cycle times of less than 2 seconds.

In an effort to control the introduction of gas into the process chamber and thus reduce sidewall roughness, Unaxis Semiconductors (Trübbach, Switzerland/St. Petersburg, FL) has developed a fast gas-switching technique that eliminates destabilizing flows, even with very short step cycles, and promotes a smooth transition between etch and deposition steps. Using the fast gas-switching technique, the times required to perform those steps can be reduced to the limiting value of the gas residence-time constants of the processing module. More-rapid etch rates resulting in smoother sidewalls can be achieved by avoiding wait steps for pressure stabilization.

Figure 3: The effects of gas flow on scallops: (a) schematic diagram of sidewall scallop length and depth, and (b) chart showing the etch rate for conventional Bosch process (blue plots) versus an improved etch rate with the fast gas-switching method (purple plots). The latter technique also improves sidewall smoothness.

Because sidewall scallops are easy to measure, the distance between them is used to measure their depth or amplitude. The illustration in Figure 3a highlights the relationship between scallop length and depth, while Figure 3b illustrates the correlation between the length of sidewall scallops and the etch rate. As shown in Figure 3b, the distance between the scallops in conventional Bosch processing increases as the etch rate increases. In contrast, the fast gas-switching technique enables processing at faster etch rates without a corresponding increase in scallop length. Moreover, faster etch rates do not increase sidewall roughness. The scanning electron microscope (SEM) images in Figure 4 show that this technique results in smooth sidewalls. Using the technique, etch rates of ~7 µm/min are possible with 100-µm-wide trenches, and etch rates >4.5 µm/min are possible with trenches as small as 2.5 µm wide. Process times around a half second, limited only by the residence-time constant of the module, can be implemented without expensive hardware.

Process Pressure Control

The cyclical nature of deep silicon etching places unique demands on common methods of pressure control. Accurately tracking pressure during etch and deposition steps is difficult without suitable control logic. Because of their response lag, throttle valves do not respond well to the pressure setpoints of individual steps without inducing either pressure drift or overshoot. While open-throttle-position control solves the problem partially, that method still results in drift and poor wafer-to-wafer reproducibility during long processes. As shown in Figure 5a, when an open-throttle-position control method is used, pressure drifts considerably and continues to move out of compliance even over a relatively short process time.

Figure 5: Laboratory tests involving (a) pressure control using throttle-position setpoints shows typical drift, and (b) pressure control using an algorithm combining pressure and throttle-position control shows long-term pressure stability.

In order to provide a stable processing environment that avoids pressure drift and overshoot, a proprietary algorithm has been developed that uses a combination of both closed-loop pressure control and throttle-valve positioning. The ability of that method to maintain accurate and stable process pressure is demonstrated in Figure 5b.

SOI Endpoint Detection

Aspect-ratio-dependent etching occurs when features of different dimensions are etched. As aspect ratios (feature etching depth divided by width) increase, the mass transfer of reagents and etching by-products in and out of the etched feature becomes a limiting factor. Hence, etch times for high-aspect-ratio features are slower than those for low-aspect-ratio features. This characteristic affects SOI processes because large features (those with lower aspect ratios) etch to the oxide insulator layer before small ones. As larger features wait for the smaller ones to reach the oxide layer during overetch, the larger features may experience unwanted notching at the oxide-silicon interface.

Figure 6: SEM image of an SOI test structure showing a considerable range of feature widths from 2.5 to 100 µm, resulting in aspect ratios of ~20 down to 0.5.

To counteract the effects of overetching in SOI processes, a sensitive method of endpoint detection is required to detect small amounts of oxide exposed during the etch process. With endpoint detection, the SOI finish-etch step can occur as early in the process as possible. Figure 6 shows a process development pattern used to study endpoint capabilities on SOI wafers. An appropriate endpoint-detection technique can accommodate a wide range of aspect ratios.

Because of the cyclical nature of deep silicon etching, the conventional endpoint-detection methods of laser reflectance interferometry and optical emission spectroscopy (OES) lack sufficient sensitivity. However, with signal processing methods, as little as 2% open oxide areas on 150-mm wafers can be detected. Figure 7 shows an unambiguous endpoint signal that can be extracted using signal processing methods from the wide variations of intensities emitted during etch and deposition steps.

Figure 7: OES endpoint signal from SOI etch process, with 2% oxide exposed on 150-mm wafer. The blue plots indicate the raw OES input data, and the orange line indicates the OES algorithm.

Applying Deep Silicon-Etch Technology

Although well-known MEMS applications such as ink-jet printers, pressure sensors, and airbag deployment accelerometers have demonstrated distinct performance advantages and market penetration, other, lesser-known applications have been successful as well. For example, one nontypical MEMS application involves the use of microactuators to effectively increase performance in hard-disk drives.⁴

Seagate Technology (Scotts Valley, CA) has applied a MEMS process to manufacture an inexpensive microactuator that has a small device mass, is easily integrated into a thin-film head structure, and maintains mechanical and electronic compatibility with the other drive components. The resulting design is manufactured in a wafer-level batch process that uses bulk silicon micromachining and includes high-aspect-ratio structures. With device etching depths ranging from 50 to 200 µm, relatively high etch rates are necessary to achieve adequate throughput. The microactuator has features ranging from narrow channels that serve to define springs to large areas that accommodate attached device components. Although the range of feature sizes and the requirement that profiles be vertical can be satisfied with the use of morphing, that technique is not required to produce the device. A SEM image of the deep silicon-etched portion of the microactuator is shown in Figure 8a, while a magnification of the lower right-hand corner of the device is shown in Figure 8b. Table II provides a summary of some of the etching characteristics involved in the microactuator's fabrication.

Figure 8: Microactuator frame fabricated with a deep silicon-etch technology: (a) entire frame, and (b) magnified image of the frame's lower right-hand corner.

Conclusion

This article has described advances in deep silicon-etch processing and system components that encourage MEMS development and commercialization efforts. Moving deep silicon-etch processes from the exploration phase into production presents many challenges that go beyond the basic etch step. This article has focused on several manufacturing issues, including fast etch rates to achieve high throughput, sidewall smoothness to achieve device performance, pressure control for long-term process stability and reproducibility, and sensitive endpoint detection in SOI processing steps.

Process Paramater Value Description Etch rate 6.5 µm/min Low-aspect-ratio features Within-wafer uniformity ≤+2.5% (max – min) 2 X average for 100-mm wafers Selectivity ~600:1 Si:SiO2 Sidewall angle 90° ± 1° —

Table II: Summary of the deep silicon-etch process results optimized for Seagate's microactuator application.

The article has also discussed processes that produce extremely smooth sidewalls with roughness of <10 nm, a degree of surface smoothness that can be maintained with silicon etch rates >7 µm/min. Volume production often emphasizes etch rates as a route to lowering costs and increasing throughput. Significantly higher rates can be achieved for applications in which silicon etch rates and feature profile are of greater importance than sidewall morphology. However, increased etch rates are often accompanied by higher initial capital costs, which must be considered in the context of market size and dynamics.

Because there are always trade-offs between performance and capital costs, the required process capability and production volume must be well matched. To accommodate performance, volume, and cost needs, vendors have introduced manual load or cassette-to-cassette systems with the appropriate hardware to support desired processes.

Acknowledgments

This article is based on a presentation given at the Eighth International Conference on the Commercialization of Micro and Nano Systems (COMS), held September 8–11, 2003, in Amsterdam, The Netherlands.

References

1. "Etching Process for Producing Substantially Undercut Free Silicon on Insulator Structures," U.S. Pat. 6,071,822, June 2000.

2. "Morphed Processing of Semiconductor Devices," U.S. Pat. 06,417,013, July 2002.

3. M Blauw et al., "Balancing the Etching and Passivation in Time-Multiplexed Deep Dry Etching of Silicon," Journal of Vacuum Science and Technology B 19 (2001): 2930–2934.

4. R Hipwell et al., "Hard Disk Drive Performance Enhanced by MEMS Devices," Solid State Technology 46, no. 5 (2003): 75–78.

---

David G. Lishan, PhD, is a principal scientist at Unaxis Semiconductors in St. Petersburg, FL, where he has been responsible for various etch and PVD processes for semiconductor and thin-film-head applications. His nearly 30 years of research and industrial experience includes photochemistry, III-V etching, and PVD. He has produced more than 25 publications. He received a BS in chemistry from the University of California, Santa Cruz, and a PhD in solid-state electrical engineering from UC Santa Barbara. (Lishan can be reached at 727/577-4999 or david.lishan@unaxis.com.)

Russ Westerman is a principal engineer at Unaxis Semiconductors in the compound semiconductor business unit, where he focuses on hardware and process development for plasma etch processes. He has coauthored more than 15 papers on topics ranging from MEMS etching, photomask etching, compound semiconductor etching, and InP and GaAS processes. He received a BS in chemical engineering from Virginia Polytechnic Institute and State University (Blacksburg) in 1989, an MS in chemical engineering from the University of Illinois (Urbana-Champagne) in 1994, and an MBA from Florida Institute of Technology (Melbourne) in 2000. (Westerman can be reached at 727/577-4999 or russ.westerman@unaxis.com.)

Shouliang Lai, PhD, is a senior process engineer at Unaxis Semiconductors. He received a PhD in electronics materials from the University of Illinois (Urbana-Champaign) in 1998. (Lai can be reached at 727/577-4999 or shouliang.lai@unaxis.com.)

Abdul Lateef is a senior process engineer at Unaxis Semiconductors. He has been involved in plasma processing and applications development for semiconductor, planer wave-guide circuit, and thin-film-head applications. He has coauthored several papers in these fields. He received a BS in mechanical engineering in 1992 and an MS in materials science in 1996 from the University of Nebraska in Lincoln. (Lateef can be reached at 727/577-4999 or abdul.lateef@unaxis.com.)

Mike DeVre is an applications manager at Unaxis Semiconductors. Previously, he spent 17 years at General Electric, where he held various engineering positions primarily in the areas of plasma and semiconductor processing in the company's research and aerospace electronics divisions. He has authored or coauthored more than a dozen papers in the thin-film technology area and holds six patents. In 1979 he received an AAS degree in electrical technology, and in 1986 he received a BS in electrical engineering from Union College in Schenectady, NY. (DeVre can be reached at 727/577-4999 or mike.devre@unaxis.com.)

David Purser is an applications engineer at Unaxis Semiconductors, where he has worked for three years in the area of deep silicon-etch techniques. He has coauthored several papers in this field. He received a BS in electrical engineering in 1998 and an MS in the same field in 2001 from the University of North Carolina in Charlotte. (Purser can be reached at 727/577-4999 or david.purser@unaxis.com.)

David Johnson, PhD, is the R&D director at Unaxis Semiconductors, where he has been for 25 years. Initially in charge of the applications laboratory, he is now responsible for the development of new etch and deposition technologies for use in semiconductor and related areas. Johnson was a postdoctoral researcher at the University of Florida (Gainesville) in the use of atomic and molecular fluorescence spectroscopy as trace analysis techniques. He has published more than 40 papers in the areas of analytical spectroscopy and semiconductor processing and is coinventor of three patents. He received a BS in chemistry in 1970 and a PhD in analytical chemistry in 1973 from Imperial College in London. (Johnson can be reached at 727/577-4999 or david.johnson@unaxis.com.)