Testing the use of purge gas in wafer storage and transport containers

Marc Veillerot, Adrien Danel, Sybil Quiais-Marthon, and François Tardif, CEA/LETI

One of the main challenges facing microcontamination control in advanced fabs is airborne molecular contamination (AMC). Reported examples of the detrimental impact of AMC on IC devices include metal corrosion by acid gases and the poisoning of chemically amplified resins by volatile amines.^1,2 Perhaps one of the most worrisome challenges, however, is the degradation of gate oxide integrity caused by organic contamination.^3–5 Primarily because AMC has a polymorphous nature—that is, it involves a wide range of compounds, concentrations, and volatility levels—its damage mechanisms and hazard thresholds in all of these cases are not yet clearly defined.

For many reasons, fabs are increasingly using minienvironments, a trend that will be unavoidable as 300-mm manufacturing expands. In addition, automated wafer containers such as standard mechanical interfaces (SMIFs) and front-opening unified pods (FOUPs), which are designed to be compatible with equipment interfaces and help prevent contamination during storage and transport, are becoming more and more prevalent. However, wafer isolation is still problematic because boxes are enclosed, plastic, and porous environments that can concentrate contaminants, particularly organic compounds. To address that problem, manufacturers have been attracted to the use of inert and pure gas to purge storage and transport boxes in sensitive manufacturing applications, hoping to control the air environment of enclosed wafers.

This article summarizes recent efforts to explore the benefits of storing wafers in purged containers. The study described in the article focused on gate oxide storage conditions and on the impact of organic contamination originating from storage boxes. Several experiments were performed involving various combinations of storage containers and purge-gas conditions.

The Impact of Purge Gas on the Intrinsic Electrical Performance of MOS Capacitors

To measure the impact of different storage and purge-gas conditions on gate oxide integrity, wafers were stored for an extended period before polygate deposition and gate oxide and were introduced in the MOS capacitor manufacturing process. The effect of wafer storage was then examined by comparing the electrical performance of capacitors from wafers that had been stored in different types of containers.

Figure 1: Three types of storage containers used in organic contamination experiments: (a) conventional polypropylene box, (b) single-wafer FOUP, and (c) quartz container.

Three types of containers, illustrated in Figure 1, were tested. The simplest one was a standard polypropylene box. The second type was a FOUP for One from Incam Solutions (Grenoble, France), which is made of low-outgassing polycarbonate material and internally coated with a silica layer to further reduce outgassing. Two such containers were configured with purge-gas connectors, while several others were left in their original sealed form, in which they have a breathing filter that allows them to accommodate to room-pressure variations. Finally, in order to determine to what degree the plastic materials used in the first two types of containers contribute to contaminant formation, a home-made airtight, inorganic quartz container was tested. Designed with two ports to allow for the intake and outtake of purge gas, this container can hold 25 200-mm wafers. All three types of containers were cleaned in the same manner with surfactant and then rinsed.

Figure 2: Organic contamination of a 65-L process air sample. The contamination level was <2 pbbv for the sum of organic compounds and <400 pptv for the predominating compound (toluene).

Two types of purge gases were used: ultrapure dry process nitrogen and air. For both gases, a point-of-use filtration stage was used to control humidity, organic contamination, and particles. Organic contamination levels were sampled and measured using Tenax sorbent tubes and then analyzed using gas chromatography mass spectrometry (GC-MS), an organic contamination analytical procedure. As shown in Figure 2, very low levels of whole organic contamination, <2 ppbv for air and 300 pptv for nitrogen, were achieved. (The calibrating compound was n-hexadecane [n-C₁₆]).

The capacitor devices used for the tests were processed on 200-mm silicon wafers. They consisted of thin, 4.5-nm thermal silicon oxides processed at 750°C covered by a 350-nm polysilicon layer processed at 600°C. The oxidized wafers were stored in the three types of containers for 12 days before polygate deposition was performed. Then the wafers were patterned and the MOS capacitors were tested.

In the first test, the intrinsic electrical performance of devices from the wafers that had been stored in the standard polypropylene box, the purged and sealed single-wafer FOUPs, or the quartz container were compared. The single-wafer FOUPs were purged with 2 L/min of air, while the quartz container was purged with 0.2 L/min of air. This test was repeated five times to achieve a statistically significant result.

Figure 3: Intrinsic electrical performances of 4.5-nm gate oxides after 12 days of storage between oxide growth and polygate deposition. (The error bars indicate standard deviations from an average of five wafers.)

Intrinsic electrical performance results from the tests are presented in Figure 3, which shows the charges to breakdown (QBD) of small-area capacitors (0.07 mm²), based on a mean value of five wafers per container and 74 capacitors per wafer. The results have been normalized against the sealed single-FOUP box, since that container always achieved the best QBD results. Unexpectedly, all devices from wafers that had been stored under purged conditions demonstrated lower intrinsic electrical performance than devices from wafers that had been stored in unpurged containers. Moreover, there was no significant difference between the two purged containers. An additional test under the same storage conditions using nitrogen as the purge gas had the same results. These tests revealed that the purged storage container is less efficient than the sealed ones.

Parameter Impact

The investigators hypothesized that the QBD degradation observed on devices from wafers stored in the purged containers was primarily caused by the purge-gas flow effect rather than by other parameters. To confirm that hypothesis and to determine the sensitivity of the silicon oxide/polysilicon interface to the flow of purge gas, two experiments were conducted, both of which were performed only once.

Figure 4: Impact of air purge flow rate on intrinsic electrical performance of 4.5-nm gate oxide. (The error bars indicate standard deviations from an average of five wafers.)

In the first experiment, one sealed single-wafer FOUP was compared with two single-wafer FOUPs that were purged with air at two different flow rates (2 L/min versus 0.2 L/min). The purpose of the experiment was to investigate the flow rate of the purge gas inside the container, since intrinsic electrical performance was expected to correlate with that parameter. Indeed, higher gas flow rates carry greater amounts of contamination to the wafer surface, affecting electrical performance. The results from this experiment, shown in Figure 4, indicate that both purged containers had lower QBD values than the sealed container.

Figure 5: Impact of air purge humidity on intrinsic electrical performances of 4.5-nm gate oxide. (The error bars indicate standard deviations from an average of five wafers.)

In the second experiment, the effect of the purge gas's relative humidity (RH) was examined. This experiment compared the QBD of devices from wafers that had been stored in a sealed container with those from wafers that had been stored in two different single-wafer FOUPs. Although both FOUPs had been purged with air at a flow rate of 0.2 L/min, the air in one of the FOUPs had a water content at room temperature of <10% while the air in the other had a water content of 50%. Moisture control was achieved by diluting dry gas with moist gas. As illustrated in Figure 5, the devices from the container with the moister air performed better than the devices from the container with the dryer air, but the devices from the sealed container performed better than those from either purged container.

Wafer Surface Organic Contamination

Although QBD levels were shown to be a function of the gas flow rate and moisture level in the purged containers, these factors alone did not explain why the purged containers had such a detrimental impact on the device's intrinsic electrical performance. The investigators suspected that residual organic contamination from the purge gas was the main source of device degradation. Consequently, the study focused specifically on organic contamination and its characterization.

Two complementary techniques were used to identify and quantify organic components deposited on the wafer surface. First, ellipsometry was used to map organic contamination. Ellipsometry detects the deposition of organic compounds rapidly, sensitively, and accurately as a change in the apparent optical thickness of the oxide layer.⁶ First, thin, 2.5-nm silicon oxides were prepared at 950°C on 300-mm wafers. The wafers were then stored in a single-wafer FOUP that was purged with nitrogen at a flow rate of 2 L/min. For comparison purposes, wafers processed the same way were stored in a 300-mm polycarbonate shipping box.

Figure 6: Apparent thickness increase (in Å) of a 2.5-nm oxide after 48 hours of storage in (a) a single-wafer FOUP under continuous nitrogen purge at a flow rate of 2 L/min purge, and (b) a sealed polycarbonate storage box. (The arrows indicate inlet and outlet of purge-gas flow.)

After the wafers had been stored for 48 hours, nine different positions on the wafer surface were scanned and changes in the thickness of the oxide layer monitored. The results of this test are presented in Figure 6. Relatively similar increases in oxide-layer thickness were observed on the wafers from both storage containers, indicating the presence of similar whole organic contaminants. However, while outgassing from plastic materials was expected to be the main source of contamination in the sealed polycarbonate storage box, purge gas was expected to be the source of organic compounds in the single-wafer FOUP. These assumptions are partially confirmed by the oxide thickness distributions in Figure 6. The distribution of thickness changes on wafers from the sealed storage box was relatively homogeneous, while the distribution of thickness changes on wafers from the purged container was not, reflecting the direction of gas flow, especially near the purge gas inlet.

To characterize more accurately the nature and amount of organic contamination deposited on the wafers, thermal desorption GC-MS measurements were performed. Thin,
7-nm oxides were grown on 200-mm wafers at 750°C and then stored for 12 days in either the standard sealed polypropylene box, the sealed single-wafer FOUPs, the FOUPs that had been purged with 2-L/min of gas, or the unpurged quartz container. After storage, the wafers were desorbed inside a homemade thermal desorption chamber and organic compounds were analyzed using GC-MS.⁷ The measurement procedure followed American Society for Testing and Materials recommendations (400°C thermal desorption and contamination quantification using n-hexadecane [n-C₁₆] as the calibrating compound).⁸

Figure 7: Organic contamination measured on 200-mm oxidized wafers stored for 12 days under different storage conditions. (The dashed line represents the 2007 ITRS contamination recommendation.)

The results of the test, expressed in contamination levels per wafer area, are presented in Figure 7. They show that a rough correlation exists between the level of surface organic contamination and the intrinsic electrical performance of capacitors, as presented in Figure 3, which indicates that wafers in the sealed FOUPs (the least contaminating container) had the best QBD levels. In contrast, the containers subjected to continuous purging had the highest contamination levels and some of the worst QBD levels. Despite these correlations, the investigators were unable to discover any significant quantitative data to back up their conclusions. While wafers in the sealed quartz box appeared to have the lowest levels of organic contamination, that box did not meet requirements set by The International Technology Roadmap for Semiconductors (ITRS).⁹ The contamination levels associated with the box appeared to stem from its lack of a tight seal.

Specific storage conditions generated specific types of contaminants. The main compounds detected on wafers stored in the purged single-wafer FOUP and the sealed polypropylene box are shown in Figure 8. The compounds associated with the FOUP were caused by the air used as the purging gas and by material outgassing, while the compounds associated with the polypropylene box were caused primarily by material outgassing and to a lesser degree by cleanroom air (such boxes are not airtight).

Figure 8: Organic contamination measured on 200-mm oxidized wafers stored for 12 days in (a) a standard sealed polypropylene box, and (b) a single-wafer FOUP under constant airflow of 2 L/min. Contamination levels were 7.87 X 1013 and 1.47 X 1014 at.C/cm2, respectively.

As expected, the two types of boxes generated significantly different chemical species. Although the contamination levels on wafers from the single-wafer FOUP were twice that of the levels on wafers from the polypropylene box, the wafers from both boxes did not have significantly different QBD levels. Hence, not only contamination levels, but also the types of contaminants, must be considered when establishing contamination control protocols. Since the ITRS considers global contamination levels without addressing the types of contaminants, research is still required to understand the effects of organic contamination on advanced microelectronic devices.

Conclusion

While the use of minienvironments and automated containers is spreading in the IC manufacturing industry, the damage such enclosed environments can cause, even when purged, is worrisome. Based on the specific case of gate oxide preservation, this article has demonstrated that using a purge gas in storage containers is problematic. Indeed, the use of a dry purge gas or residual organic contamination, which is present even in purified gas, can have a detrimental impact on electrical device performances.

The experiments presented in this article demonstrate that not all container materials have a similar effect on the wafers stored in them. Although new-generation containers, such as single-wafer FOUPs, ensure better storage conditions than conventional polypropylene boxes, not even sealed quartz containers meet ITRS recommendations for long-term storage.

Finally, the tests discussed here indicate that the qualitative nature of organic contamination has at least as much of an impact on intrinsic electrical device performance as the quantitative amounts of organic contaminants present on the wafer surface. Unfortunately, the qualitative nature of organic contamination has yet to be seriously considered in efforts to determine hazard thresholds.

Acknowledgments

The authors would like to thank Incam Solutions for providing storage containers and technical information about their products. The authors also wish to acknowledge medea+ for providing financial support for this project.

References

1. SJ Lue et al., "Application of Ion Chromatography to the Semiconductor Industry. I: Measurement of Acidic Airborne Contaminants in Clean Rooms," Journal of Chromatography A 804 (1998): 273–278.

2. KR Dean et al., "Effects of Airborne Molecular Contamination on DUV Photoresists," Journal of Photopolymer Science and Technology 10, no. 3 (1997): 425–444.

3. S de Gendt et al., "Impact of Organic Contamination on Thin Gate Oxide Quality," Japanese Journal of Applied Physics 37, no. 9A (1998): 4649–4655.

4. M Claes and S de Gendt, "Organic Contamination: Impact, Characterization, Sources and Cleaning during IC Manufacturing," in Proceedings of DECON 2001 (Pennington, NJ: Electrochemical Society, 2001), 320–335.

5. F Tardif et al., "Hydrocarbons Impact on Thin Gate Oxides," in Proceedings of the International Symposium on Ultra Clean Processing of Silicon Surfaces (Leuven, Belgium: Acco, 1996), 309–312.

6. A Danel et al., "Dry Cleaning of Organic Contamination on Silicon Wafers Using Rapid Optical Surface Treatment," in Proceedings of the International Symposium on Ultra Clean Processing of Silicon Surfaces (Leuven, Belgium: Acco, 2000), 59–62.

7. M Veillerot et al., "Deposition Kinetic of Airborne Organic Contamination on Wafers Measured by TD-GCMS" (paper presented at the European Materials Research Society 2002 Spring Meeting, Strasbourg, France, June 18–21, 2002).

8. "Standard Test Methods for Analyzing Organic Contaminants on Silicon Wafer Surfaces by Thermal Desorption Gas Chromatography," Standard F-1982 (West Conshohocken, PA: American Society for Testing and Materials, 1999).

9. The International Technology Roadmap for Semiconductors (San Jose: Semiconductor Industry Association, 2001); available from Internet: http://public.itrs.net.

Marc Veillerot, PhD, is a research engineer at the Commissariat à l'Energie Atomique/Laboratoire d'Electronique de Technologie d'Information (CEA/LETI) in Grenoble, France, where he works on silicon surface characterization and focuses on airborne molecular contamination. He spent eight years working in the field of atmospheric chemistry at the French National Air Pollution Laboratory. He received an engineering degree in material chemistry in 1992 and a PhD in process engineering in 1996 from the National Polytechnical Institute of Grenoble. (Veillerot can be reached at +33 4 38784193 or marc.veillerot@cea.fr.)

Adrien Danel, PhD, is a research engineer at CEA/LETI, where he works with silicon surface characterization by noninvasive methods and focuses on advanced cleaning processes. He received an engineering diploma in 1994 and a PhD in in physics and microelectronics in 1999 from the National Polytechnical Institute of Grenoble. (Danel can be reached at +33 4 38782069 or adrien.danel@cea.fr.)

 

Sybil Quiais-Marthon is manager of the optics, x-rays, and surface characterization lab at CEA/LETI. Until 2000 she worked as a specialist in microcontamination analysis in the field of semiconductor manufacturing and was involved in advanced material characterization. She has more than 15 years of experience in several areas of analytical instrumentation, including microscopy, surface analysis, and chemical analysis. She received a degree in technical engineering from Joseph Fourier University in Grenoble. (Quiais-Marthon can be reached at +33 4 38783231 or sybil.quiaismarthon@cea.fr.)

François Tardif, PhD, heads the ultraclean process laboratory in the microelectronics department at LETI. A member of the Electrochemical Society, he has coorganized congresses in the fields of silicon cleaning and ultratrace contamination measurements and has authored more than 50 papers. He graduated from the engineering school of L'Institut National des Sciences Appliquees in Toulouse and received a PhD in materials science from the University of Marseille. (Tardif can be reached at +33 4 38783332 or fran&ccedil;ois.tardif@cea.fr.)