Removing gold seed-layer materials using reactive ion etch

Paul Werbaneth, Tegal; and Tim Lester and Jadwiga Pakulska, Nortel Networks

A variety of metals can be used for interconnect metallization in IC and MEMS device fabrication. Aluminum and aluminum alloys, tungsten, copper, platinum, and gold are all employed as thin-film conductors in microelectronic device fabrication. Manufacturers choose which material to use for specific applications based on the many different electrical and mechanical properties that must be optimized to fabricate conductor layers or to perform interconnect tasks. These essential properties include film electrical resistivity, mechanical and chemical stability, adhesion characteristics, film deposition characteristics, and the ease with which films can be patterned. When used as interconnect materials, copper and gold have several notable performance advantages: they offer low resistivity (1.7 µΩ-cm and 2.2 µΩ-cm, respectively) and prevent electromigration-related failures.¹ To ameliorate resistance-capacitance delay issues, which degrade overall device performance, copper is widely used as the material of choice for interconnects in leading-edge CMOS ICs.

While gold is seldom used for interconnect metallization in silicon-based devices (except in backside metallization processes), it is used extensively in MEMS and compound semiconductor device fabrication and in wafer packaging applications because of its high electrical conductivity and its relative chemical inertness.² Gold interconnects are also compatible with the semiconductor contact metallurgies and gate metal stacks typically used in compound semiconductor devices.

Typical gold thicknesses used in MEMS, compound semiconductor, and packaging applications are 3, 20–30, or 4.5 µm.^3–5 Generally, gold is deposited on top of an adhesion-promoting or a diffusion barrier layer commonly composed of titanium, tungsten, or platinum. Since electroplating achieves excellent pattern fidelity while conserving the expensive starting material, it is the standard method for depositing gold films. Consequently, in addition to adhesion-promoting and diffusion barrier layers, a thin layer of gold or platinum seed metal is almost always deposited before the bulk of the gold is electroplated. On normal topographies, at least 100 nm of seed metal are required to achieve low resistance and uniform plating.

Since the goal of the interconnect process is to form independent, distinct, electrically isolated conductive lines of gold, one of the final process steps in an electroplated gold interconnect process module, after electroplating has occurred and the electroplating mask has been stripped, is the removal of the seed layer and the diffusion barrier/adhesion-promoting stack. Removal of this electrically conductive metal stack effectively isolates the metal interconnect lines formed during electroplating, freeing them to perform their designated tasks. Figure 1 shows a schematic of an electroplated structure before and after the etching of the seed layer.

Figure 1: Schematic diagrams of electroplated structure (a) before and (b) after seed-layer etch.

Fabricating gold-plated interconnects in compound semiconductors often does not require a barrier layer, but adhesion promotion is still important. For example, in some cases a 10-nm titanium adhesion layer followed by 100 nm of gold deposited by evaporation or sputtering would be sufficient to perform the plating process. In practice, however, a more-complex seed-layer stack (i.e., the entire seed layer/diffusion barrier/adhesion-promoting stack) may be required to overcome problems encountered during the seed-layer removal process.

Several standard techniques are available for removing seed layers following electrodeposition, each of which has characteristic strengths and weaknesses that come to light when seed-layer film removal processes are employed in volume production. Three such methods are wet processing, reverse plating, and reactive ion etch (RIE). This article demonstrates that the use of RIE to remove seed-layer materials is an attractive alternative to the other standard methods. It highlights the important differences between the approaches and demonstrates that RIE in a high-density plasma reactor is more effective than the other techniques for removing gold seed layers.

Wet Processing

Wet processing is commonly used to remove gold seed layers from MEMS and compound semiconductor devices. However, while wet processing can remove seed layers, it undercuts the plated gold line (possibly reducing its mechanical integrity), does not remove the layer uniformly, causes excessive loss of plated metal, raises environmental and safety issues related to the use of wet-etch chemistries, and is expensive.

Early attempts at Nortel Networks (Nepean, ON, Canada) to remove a simple Ti/Au seed layer by wet etching proved unsuccessful. It was found that both potassium iodide (KI)–based etches and commercially available cyanide-based chemistries etched the plated gold two to three times faster than the evaporated or sputtered seed gold. The plated metal also became very rough as its grain structure was delineated. That result prompted an investigation into the use of reverse plating to remove the gold portion of the seed layer.

Reverse Plating

In order to remove the gold portion of the seed layer by reverse plating, an underlying conductive layer is required to supply the current. In the absence of such a layer, nonuniform removal rates cause traces of seed layer to be left in regions that become disconnected electrically from the contacts at the periphery of the wafer. Therefore, the adhesion/barrier portion of the seed layer stack must be able to function independently as a reliable conducting layer over any existing topography. That layer must be removed by means of a separate process step.

Reverse plating is generally performed at constant current, and the voltage can be monitored to detect the endpoint. In early reverse-plating efforts at Nortel, the wafer was clipped onto a polypropylene plate using eight contacting clips and then fully immersed in a recirculating bath. Subsequently, the process was carried out in an automated single-wafer system that incorporated a fountain deplate head and a rotating wafer holder with pins that gripped the edge of the wafer and contacted the seed layer. As recommended by the tool manufacturer, only one electrolyte (a solution of thiourea, NH₂CSNH₂) was investigated.

Figure 2: SEM images of center and edge of wafer with (a) reverse plating time optimized for the wafer center, and (b) excessive etching of the metal feature at wafer edge.

The Gold Reverse-Plating Process. Unlike wet etching, reverse plating removes the seed gold at about the same rate as the plated gold. However, the gold continues to be electrochemically etched once the underlying conducting layer has been reached. In fact, experiments found that at a constant current, the removal rate of the plated gold lines increases significantly once most of the gold seed layer has been cleared. That effect is severe for isolated features, where the nonuniformity of the reverse-plating process becomes a critical issue. As shown in the SEM images in Figure 2, when reverse-plating time is optimized for the center of the wafer, the edge experiences excessive etching.

To complicate matters, interconnect lines in compound semiconductor circuits are typically many microns thick, and the seed-layer removal rate is slightly lower in the high-aspect-ratio gap between two closely spaced metal lines. Consequently, an extended reverse-plating step is required to clear these regions, which also results in excessive removal of the plated lines.

Figure 3: Reverse-plating endpoint traces for three different metal patterns (product codes).

Typical endpoint signals during reverse plating are presented in Figure 3. Even after deplate uniformity has been optimized, endpoints are not very abrupt and can vary significantly with the overall density of the interconnect on the wafer. Overall, there is very little process margin for reverse plating of the seed layer. Therefore, extended deplate times must be fine-tuned for different metal patterns (product codes).

Increasing the Thickness of the Titanium Adhesion Layer. Increasing the thickness of the titanium adhesion layer to 30 nm can provide the needed conduction to reverse-plate the gold. However, great care must be taken not to create breaks in this layer, particularly at the die periphery, where scribe line etches can create large amounts of topography. At Nortel, the investigators found that replacing hot O₂ downstream ashing of the plating resist with wet strips and a room-temperature O₂ descum procedure in a parallel-plate RIE tool can prevent such breaks.

The remaining thin titanium layer can be removed using wet chemical etching in hot phosphoric acid, or dry etching with fluorine- or chlorine-containing plasmas. Wet etching of a simple titanium base layer is problematic. A frilly, very tenuous network of seed layer, caused by the diffusion of gold into the grain boundaries of the titanium, often remains after etching, requiring that a final dilute KI gold etch be performed to remove the frills. Since Ti/W sputtered from a compound target does not suffer from the gold diffusion problem, it can be etched away cleanly in 60°C peroxide. Unfortunately, it was found that Ti/W has a tendency to undercut, as illustrated in the SEM images in Figure 4. On occasion, such undercutting was severe enough to cause the narrow interconnect lines to lift.

Figure 4: Undercutting of TiW layer after H2O2 wet etch.

In contrast, dry etching offers the advantage of reducing Ti layer undercutting, but it can cause stringers to remain along vertical edges or grooves in the underlying topography because of the directionality of the etch. Initial attempts to dry etch the titanium adhesion layer eventually prompted Nortel to adopt the method of planarizing the underlying topography to prevent residual stringers.

Figure 5: Diagram of the dual-frequency, high-density plasma reactor.

Using RIE to Remove Seed Layers

Plasma Reactor Configuration. The limitations of using wet processing or reverse plating to remove the seed-layer from compound semiconductor devices led Nortel to investigate the use of plasma reactors for seed-layer removal. The work discussed in this article was performed using a 6520 dual-frequency plasma reactor from Tegal (Petaluma, CA). The reactor is illustrated in Figure 5, and a top view of the system platform showing two etch reactors, a plasma strip module, and a wet-rinse station is shown in Figure 6.

Figure 6: Top-view diagram of the plasma reactor system platform, showing two etch reactors, an inductively coupled plasma (ICP) strip module, and a wet-rinse station.

Once Nortel had decided that dry etching would be successful if the topography underneath the seed layer were planarized to eradicate residual stringers, a process using high-density-plasma etching of the full seed-layer stack was considered. Work at Tegal had already resulted in the successful pattern etching of platinum and gold layers using a version of the high-density plasma reactor shown in Figures 5 and 6. Work at Nortel qualified the reactor for dry etching of seed-layer metals. That qualification resulted from tests to determine the etch rate of exposed metals during other compound semiconductor plasma etching steps. Only a few samples were etched because of chamber contamination concerns, but preliminary results indicated that the reactor could be used successfully to etch the gold portion of a seed layer and that it might also be able to handle thin platinum layers, as indicated in Figure 7.

Figure 7: RIE plasma etch rates of various isolated metal features on a GaAs substrate.

The plasma etch of gold and platinum generally relies on a strong physical etch component provided by surface bombardment of the wafer with energetic ions from the plasma, and a reactive etch component (chiefly halogen radicals created in the plasma).^{6, 7} Table I lists the elements most often found in seed-layer stacks and the halogens used to etch them in plasma reactors. Since titanium and tungsten etch readily in fluorine chemistries without much ion bombardment, the plasma reactor used to etch different films must be optimized in order to achieve independent control of plasma density and ion bombardment energy.⁸

Element Etchant (Plasma Reactor) Gold Fluorine, chlorine, bromine Platinum Chlorine, bromine Titanium Fluorine, chlorine Tungsten Fluorine, chlorine

Table I: Plasma etchants for seed-layer metals.

Using chlorine- and bromine-based etchants requires that the plasma reactor be isolated from the atmosphere with vacuum loadlocks. The reactants and the product compounds formed during plasma etching inevitably adhere to the walls of the plasma reactor. Should the reactor be exposed to a moist atmosphere between etches, the deposits on the reactor walls hydrolyze, resulting in the generation of potentially harmful vapors that can cause wafer-to-wafer process instability and particle-related defects. Chlorinated etch chemistries can also result in postetch corrosion.

There are many well-established techniques for preventing postetch corrosion in etched films. Usually, residual chlorine is removed immediately after etch by exposing the wafer to oxygen- or hydrogen-containing plasmas, heating the wafer under vacuum, rinsing the wafer with DI water or another aqueous solution, or performing some combination of these techniques.

Figure 8: With power set at 40 W kHz, the etching of the seed layer (consisting of a 10-nm-thick titanium film and 100-nm-thick gold film) was not clean. Resputtered metal was left on the sides of the metal lines and the seed metal on the more sloped portion of the topography was not removed adequately.

Experimental Results. The tests discussed here focused on the use of a Cl₂/helium gas mixture with or without the addition of argon. All the work was done at a fixed megahertz power setting and a fixed pressure of <10 mTorr. Initial observations indicated that even though the gold etch rate was quite high when power was set at 40 W kHz, the etching of the seed layer (which consisted of a 10-nm-thick titanium film and 100-nm-thick gold film) was not clean at that bias power level. Resputtered metal was left clinging to the sides of the metal lines, and the seed metal on the more sloped portion of the topography was not removed adequately, as illustrated in the SEM image in Figure 8. Figures 9a–9c show the improvement in seed-layer removal as power was increased to 60, 70, and 80 W kHz, respectively.

It was also found that at higher kilohertz powers, the amount of overetch required to avoid leaving metal stringers was directly related to the vertical thickness of the seed metal on sloped surfaces that had a maximum angle of about 60° from the horizontal surface. For steeper slopes, the results varied considerably. Since the thickness of seed layers deposited by sputtering is quite uniform over smoothed topographies, a slope of 60° or less requires that seed layer overetch be at least 100%.

A major concern was that as more wafers were run in the chamber, the surface leakage between lines could increase as a result of resputtering from the accumulated chamber deposits. Consequently, a special structure was included in the process control monitor to test for interline leakage. That structure was composed of interleaved fingers of a minimum-line-width plated metal at minimum pitch that was placed over a random underlying topography. Because the leakage current between the fingers after etch and a water rinse was not negligible, a special postetch treatment was devised to reduce the leakage to a level comparable to that of the reverse plating process. Subsequently, as more wafers were etched in the chamber, the leakage abated, causing no noticeable change in the appearance of the interconnect.

Since gold chloride etch products are not very volatile at moderate etching temperatures, it was anticipated that a successful production process would require a good chamber-clean strategy. Thus, removable ceramic shielding developed by Tegal was installed in Nortel's 6520 reactor. With increased shielding in place, nearly all of the chamber surfaces exposed to direct-line-of-sight coatings were protected. However, the installation of the redesigned ceramic liner produced a marked leakage spike, illustrating the need to condition new ceramic shields before they are used for production. After undergoing conditioning, the additional shielding did not alter the etch characteristics of the chamber.

The first chamber clean was triggered not by a degradation in the seed-layer etch, but by the tool's inability to detect plasma ignition because of deposits on the endpoint sensor window. Therefore, a dilute aqua regia etch (15 HCl:15 HNO₃:70 H₂O) was used to etch the gold deposits off tool windows and ceramic parts. When the chamber was returned to service, a very small increase in test-structure leakage current was noticed. After several more wafers were etched, however, the current returned to its normal value, as shown in Figure 10.

Figure 10: Postetch test structure leakage current measurements from the plasma chamber's metal isolation test structure. (The wafer count is approximate and does not include test and setup wafers. Values are wafer medians.)

Conclusion

Several standard techniques used to remove gold seed-layer films from electroplated metallization structures created during compound semiconductor device fabrication have been examined. Wet etching of the seed layer was found to be impractical because it causes excessive etching of the plated metal features and undercuts the adhesion or barrier layer. Reverse plating is too dependent on overall pattern density, making it impractical for use in a volume production fabrication line running many different product codes. The reverse-plating process also exhibits a significant loading effect; as the seed layer clears, there is a marked increase in the rate at which gold in the interconnect lines is removed, making the reverse-plating process difficult to control.

The work reported in this article on the optimization of seed-layer etching demonstrates that reactive ion etching of seed-layer materials is an excellent alternative to wet etch or reverse plating methods. Robust processes with high etch rates, good throughputs, and good electrical results can be optimized in low-pressure, high-density-plasma reactors with good repeatability over many etched wafers.

References

1. S Wolf, Silicon Processing for the VLSI Era, vol. 2 (Sunset Beach, CA: Lattice Press, 1990), 192–193.

2. R Williams, Modern GaAs Processing Methods (Norwood, MA: Artech House, 1990), 272–273.

3. J-H Park et al., "Novel Micromachined Coplanar Waveguide Transmission Lines for Application in Millimeter-Wave Circuits," Japanese Journal of Applied Physics 39 (2000): 7120–7124.

4. J Lau, ed., Flip Chip Technologies (New York: McGraw-Hill, 1996), 418.

5. J Dilley and S Hall, "A Manufacturable Multi-Level Interconnect Process Using Two Layers of 4.5 µm-Thick Plated Gold," in 2000 International Conference on Gallium Arsenide Manufacturing Technology Digest of Papers (St. Louis: GaAs Mantech, 2000), 219–221.

6. P Werbaneth et al., "The Reactive Ion Etching of Au on GaAs Substrates in a High Density Plasma Etch Reactor," in 1999 International Conference on Gallium Arsenide Manufacturing Technology Digest of Papers (St. Louis: GaAs Mantech, 2000), 31–34.

7. P Werbaneth et al., "Pt/PZT/Pt and Pt/Barrier Stack Etches for MEMS Devices in a Dual Frequency High Density Plasma Reactor," in Proceedings of the 2002 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (Piscataway, NJ: IEEE, 2002), 177–183.

8. J Coburn, Plasma Etching and Reactive Ion Etching (New York: American Institute of Physics, 1982), 78.

Paul Werbaneth is a regional marketing director at Tegal (Petaluma, CA). He has worked for more than 20 years in semiconductor process engineering and technical marketing positions at Intel, Hitachi America, and Tegal. Werbaneth is the author or coauthor of more than 35 papers and articles on all aspects of plasma etch processing. He is a member of AVS, ECS, IEEE, and SPIE, and is on the GaAs Mantech Technical Program Committee, the SEMI International MEMS Advisory Group, and the steering committee of the Advanced Semiconductor Manufacturing Conference. He received a BS in chemical engineering from Cornell University in 1979. (Werbaneth can be reached at 707/765-5608 or pwerbane@tegal.com.)

Tim Lester, PhD, is a senior member of the scientific staff at Nortel Networks (Nepean, ON, Canada), where he has spent most of his career as part of the high-speed-modules development group. He is responsible for the design and integration of processes for the manufacture of gallium arsenide and indium phosphide heterojunction bipolar transistors. He has a BS in physics from the University of Victoria, BC, Canada, and an MS in astronomy and a PhD in solid-state electronics from the University of British Columbia, Canada. (Lester can be reached at 613/763-5923 or tlester@nortelnetworks.com.)

 

Jadwiga Pakulska, PhD, works for the optoelectronics and microelectronics groups of Nortel Networks, where she is responsible for gold electrodeposition of metal interconnects for III-V semiconductor devices. She received an MS from Adam Mickiewicz University in Poznan, Poland, in 1974 and a PhD from Wroclaw Technical University, Poland, in 1984 for studies of thin oxide films on metal alloys. (Pakulska can be reached at 613/763-3610 or jadwiga@nortelnetworks.com.)