Controlling dislocations and bulk microdefects on fabricated wafers to prevent device leakage

Garth K. Su, MEMC Electronic Materials

The control of reverse leakage current in semiconductor wafers is important for reliable operation of all dynamic MOS products such as DRAM and charge-coupled devices. Leakage current is affected by a variety of material parameters:

• Metallic impurities. Silicon device fabrication at high furnace temperatures increases metallic contamination. In turn, metallic impurities, acting as recombination centers between the bandgap, decrease devices' minority carrier lifetime and increase the leakage current of p-n junctions.

• Oxygen content. Wafers grown using the standard Czochralski (CZ) technique incorporate oxygen into the bulk silicon from the crucible. Oxygen enhances gettering by forming bulk microdefects (BMDs) from precipitated oxygen atoms.

• Dislocations. A high oxygen precipitate content induces excessive lattice strain, resulting in dislocations. Dislocations, if present at the p-n junction, cause dopant diffusion pipes.¹

• Stacking faults. In addition to causing dislocations, the lattice strain induced by excessive oxygen precipitate results in stacking faults, which are associated with a dislocation loop that bounds the fault plane. Stacking faults that penetrate the p-n junctions also enhance the recombination current and consequently enhance junction leakage.²

This article, based on research performed at MEMC Electronic Materials (St. Peters, MO), discusses the influence of metallic impurities, dislocations, and oxygen content on device leakage current. In addition, the article presents a method for controlling oxygen precipitation, which is crucial for ensuring effective internal gettering.

Wafer Test Setup

The polished silicon wafers investigated in this article, grown using the CZ technique, were 150-mm p-type wafers with a <100> crystal orientation. Fabricated for a CMOS logic device, wafer A had devices with failure regions near the edge of the wafer. Wafers B and C were unpatterned bare silicon wafers. Both wafers A and B were produced by the same supplier using the same crystal pulling and wafering processes, while wafer C was produced by another supplier. Nominally, all three wafers had the same crystal and wafering specifications. Their interstitial oxygen (O_i) level was in the range of 13.2–13.5 ppma (the ASTM F121-83 parts-per-million-atomic standard), as confirmed by Fourier transform infrared measurements. Wafers A and B were compared with wafer C, which did not exhibit device leakage at the IC manufacturing site. The characteristics of the wafers investigated during this study are listed in Table I.

WaferLabel SupplierLabel Oi Level(ppma) CrystalType Leakage A 1 13.2–13.5 I Yes B 1 13.2–13.5 I Yes C 2 13.2–13.5 II No

Table I: Oi levels and leakage characteristics of the wafers tested for the study.

The device pattern on the fabricated wafer (wafer A) was removed using 49% HF with a trace of surfactant. That procedure was followed by a Schimmel etch (1 mol of CrO₃:49% HF at a 1:2 volume ratio) for 60 seconds to delineate defects on a device surface with a P <100> crystal orientation. The etch process removed a 2.8-µm layer of silicon. Finally, an interference contrast microscope was used to inspect the wafer for etch-delineated defects.

Test Data and Results

Locating and Characterizing Wafer Defects. Using a device failure map, as illustrated in Figure 1, good and bad rows of wafer A were inspected and compared. As shown in Figure 2, a drawing was made to show the distribution of defects across the wafer surface. Clearly, the defects were located near the edge of the wafer, irrespective of the position of good and bad rows. An image of defects located in bad row 1 in Figure 1 is shown in Figure 3. The rectangular pits in Figure 3 were caused by deep-penetrating slip dislocations generated by furnace stress.

Figure 1: Leakage failure map of patterned wafer A. The 1s with circles around them indicate the five devices that failed leakage tests. The tick marks at the left and right edges show the location of the cleavage plane for BMD analysis.

The existence of the dislocations was confirmed by a cross-sectional analysis, which involved cleaving a strip from the wafer, etching the strip using a 60-second Schimmel process, and inspecting the cleaved and etched <110> surface with a microscope. The results of that analysis are visible in the image shown in Figure 4, which shows rows of slip dislocations penetrating deep into the wafer. These were caused by excessive thermal stress during furnace processing.³ Edge slip dislocations normally occur when the edge of the wafer is hotter than the center, which results when the wafer is inserted into the furnace or during temperature ramp-up.⁴ The faster the wafer insertion or the more rapid the furnace temperature ramp-up, the more pronounced the dislocation density. The presence of furnace slip dislocations near the wafer edges indicates that the slip probably took place when the wafer was being inserted into a furnace or during ramp-up to temperatures as high as 1150°C.

Figure 2: Pattern of dislocations observed on the surface of wafer A after Schimmel etch.

In addition to rectangular pits, oval-shaped pits formed at the device edges. Pictured in Figure 5, these pits were caused by dislocation loops generated during device fabrication. The pits did not penetrate deeply into the silicon substrate. Device fabrication stress can be alleviated by using a pad or buffer oxide (PadOx) to relieve the strain induced by depositing nitride films onto the underlying silicon substrate.³

The device-stress dislocations were aligned along device feature edges and nitride film edges. At the wafer edge, nitride tends to contract toward the center, while underneath the nitride, the silicon is pulled, creating dislocation loops. If the thickness of the PadOx layer falls below a critical level, the layer becomes too thin to protect the silicon underneath the oxide. A thicker PadOx layer, acting as a better buffer, can relieve excessive film stress, thus protecting the silicon without changing other electrical parameters.

Figure 3: Deep-penetrating slip dislocations (the black rectangular pits) generated by furnace stress.

It has been reported that dislocations can be electrically active and can result in junction leakage current only when they are decorated by metallic impurities. In contrast,
undecorated, "clean" dislocations have a negligible electrical effect on leakage.^5,6 That observation is consistent with the finding that leakage current was detected on wafer A, which had a low BMD density near the wafer edge, where dislocations were present. Random variations of metal concentrations across the wafer and the position of dislocations across active and nonactive device regions may further explain why leakage was found only on certain devices near the wafer edge.

Determining BMD Levels. The BMD level is associated with the oxygen nuclei formed during crystal growth and by the precipitation of those nuclei with the oxygen atoms during furnace cycles. To perform effective intrinsic gettering, the BMD level must be at least 5 X 10⁷ cm^–3.⁷ After wafer defects were located and characterized, BMDs on the cleaved surface of wafer A were counted using a microscope. Five measurements were taken at 1-cm intervals, indicating an average BMD count of 1.50 X 10⁷ cm^–3. That low count was partly a result of the smaller precipitate size from the relatively mild thermal cycles used to fabricate advanced CMOS logic devices.

Figure 4: Rows of slip dislocations penetrating deep into the wafer, caused by excessive thermal stress in the device region during furnace processing.

To study the effect of BMD density on device leakage, wafers B and C were subjected to more-severe thermal cycles. First they were annealed in a furnace under a nitrogen ambient for 4 hours at 600°C, 4 hours at 800°C, and 16 hours at 1000°C. Then they were cleaved, etched, and inspected along the cleaved and etched surface. Over five measurement points, wafer B had a BMD level of 1.85 X 10⁸ cm^–3, while wafer C had a level of 3.70 X 10⁹ cm^–3. Wafer B's BMD level was an order of magnitude higher than that of wafer A, because it underwent more-severe thermal processing. At the same time, wafer C's BMD level was an order of magnitude higher than that of wafer B. Since the same thermal cycles were used for wafers B and C, their different BMD levels must have resulted from different oxygen precipitation levels.

Figure 5: Pairs of small, black oval-shaped pits caused by dislocation loops generated during device fabrication.

Controlling Oxygen Behavior during Wafer Manufacturing

High BMD densities increase the effectiveness of gettering to remove metal contamination induced during device fabrication. To improve the gettering efficiency of these devices, a high level of oxygen precipitation is needed. This requires the effective control of oxygen behavior and BMD formation in the silicon wafer substrate. Controlling oxygen behavior is one of the most important challenges in semiconductor materials engineering.

To achieve high precipitation performance, a vacancy-concentration profile can be installed into a silicon wafer. Vacancy is a missing atom in the bulk area of the wafer. A high vacancy concentration in the bulk increases oxygen precipitation for effective gettering. Depletion of oxygen or vacancies at the surface prevent precipitation at the near-surface region of the device. As depicted in the cross-section image in Figure 6, the installation of controlled-concentration vacancy profiles, as part of the wafer-manufacturing process, can achieve an ideal distribution of oxygen precipitates, which promotes internal gettering.

Figure 6: An etched cross section of a silicon wafer with a distribution of oxygen precipitates ideal for internal gettering.

A profiled vacancy concentration enables the programming of "layered" structures, which is required for effective structure engineering by means of internal gettering. The programming of layered structures forms the basis of the Magic Denuded Zone (MDZ) method, a patented rapid thermal process–based technique in which oxygen precipitation behavior is controlled by the manipulation of vacancy rather than oxygen concentration profiles.⁸ The MDZ method induces uniform and consistent precipitation and creates a 50–100-µm-thick precipitate-free zone (PFZ) after thermal cycling (as shown in Figure 6).

The PFZ is measured as the distance from the last precipitate to the surface. PFZ depth depends on the type of measurement taken, on measurement variations, and on the thermal cycle applied to grow precipitates. Figure 7 presents an MDZ wafer using 200X magnification at the wafer center, and Figure 8 presents that wafer's PFZ feature using 500X magnification at the wafer center. To enlarge hidden precipitates not easily detected by normal methods, the wafer underwent a precipitation cycle for 4 hours at 800°C and 8 hours at 1000°C, followed by an additional cycle for 120 hours at 900°C.

Figure 7: MDZ wafer shown using 200X magnification at the wafer center.

One benefit of the MDZ method is that it is orthogonal—that is, it provides proper internal gettering nearly independent of the oxygen level required by the customer to maintain wafer strength and prevent the breakage, slip, warp, and dislocations that exacerbate device leakage. Furthermore, MDZ not only prevents device-yield upsets caused by metallic contamination, but it also improves IC makers' cost of ownership by reducing cycle times. The high density of oxygen precipitates and the deep PFZ produced by MDZ eliminates the need for additional and costly out-diffusion, nucleation, and growth thermal cycles in device makers' manufacturing lines.

Conclusion

Current leakage was found near the edge of a fabricated wafer. After device stripping and decorative etching, a dislocation pattern was observed near the edge of the wafer close to the device edges, suggesting the presence of furnace stress and device fabrication stress. In addition, these dislocations were found on both good and bad devices, indicating that device leakage was not strongly dependent on dislocations. A separate analysis showed that low BMD density led to insufficient intrinsic gettering, providing an additional source of failure.

Figure 8: The PFZ feature on the same wafer as in Figure 7, shown using 500* magnification at the wafer center.

In IC manufacturing, gettering schemes play an important role in yield management. Since the discovery of the internal gettering effect in silicon wafers 20 years ago, many scientists and engineers have encountered difficulties in controlling the precipitation of oxygen in silicon precisely and reliably. During silicon wafer manufacturing, a wafer's bulk microdefect region has a minimum density of 10⁸ cm^–3 of oxygen precipitates.⁹ The uncontrolled precipitation of oxygen in the near-surface region of the wafer can result in device leakage, which can affect yields. Reliable and efficient internal gettering requires the robust formation of surface regions that are free of oxygen precipitates (precipitate-free zones).

By reducing device leakage incidents, the MDZ method has been shown to reduce device failures and increase yields. The technique helps IC device manufacturers to minimize defect-related yield losses and to produce more good dies per wafer, boosting savings and margins in IC manufacturers' production lines.

Acknowledgments

This article is based on a presentation given at Semicon Taiwan in 2001. The author would like to thank Robert Crepin, applications lab coordinator at MEMC Electronic Materials (St. Peters, MO), and Anthony E. Stephens, coordinator of the Silicon Engineering Technology Center Laboratory at MEMC-Southwest (Sherman, TX), for their assistance in obtaining BMD measurements.

References

1. MV Whelan, "Leakage Currents of n+p Silicon Diodes with Different Amounts of Dislocations," Solid-State Electronics 12, no. 12 (1969): 963–964.

2. SP Murarka et al., "A Study of Stacking Faults during CMOS Processing: Origin, Elimination and Contribution to Leakage," Journal of the Electrochemical Society 127 (1980): 717–724.

3. BO Kolbensen and HP Strunk, "Analysis, Electrical Effects, and Prevention of Process-Induced Defects in Silicon Integrated Circuits," in VLSI Electronics Microstructure Science, ed. NG Einspruch and H Huff (Orlando, FL: Academic Press, 1985), 143–222.

4. AE Stephens, "Plastic Deformation of 200mm Silicon Wafers During Furnace Insertion and Withdrawal," in Defects in Silicon II, ed. WM Bullis, U Goeselle, and F Shimura (Pennington, NJ: Electrochemical Society, 1991), 389–397.

5. JR Monkowski, "Gettering Processes for Defect Control," Solid State Technology (July 1981): 44–51.

6. JE Lawrence, "Correlation of Silicon Material Characteristics and Device Performance," in Semiconductor Silicon 1973, ed. HR Huff and RR Burgess (Pennington, NJ: Electrochemical Society, 1973), 17–34.

7. K Sueoka et al., "Oxygen Precipitation Behavior and Its Optimum Condition for Internal Gettering and Mechanical Strength in Epitaxial and Polished Silicon Wafers," in High Purity Silicon VI, ed. CL Claeys et al. (Pennington, NJ: Electrochemical Society, 2000), 164–179.

8. R Falster, GR Fisher, and G Ferrero, "Gettering Thresholds for Transition Metals by Oxygen-Related Defects in Silicon," Applied Physics Letters 59, no. 7 (1991): 809–810.

9. R Falster et al., "The Engineering of Silicon Wafer Material Properties through Vacancy Concentration Profile Control and the Achievement of Ideal Oxygen Precipitation Behavior," in Proceedings of the Materials Research Society, vol. 510 (Warrendale, PA: Materials Research Society, 1998), 27–36.

Garth K. Su, PhD, is the global segment marketing head in the foundry, CMOS, logic, and memory segments of MEMC Electronic Materials (St. Peters, MO). He joined the company in 1997 as the project leader in the area of degradation haze. He has also been a senior engineer in the applications technology department, and the Southeast Asia applications technology head. In his current capacity, Su provides both business and technical leadership while managing the product life cycle from definition through introduction. He received MS and PhD degrees in chemical engineering from Washington University and an MBA from Fontbonne University Business School, both in St. Louis. (Su can be reached at 636/474-7851 or gsu@memc.com.)