Wet Surface Technologies

Using a single-wafer tool for wet processing
of sub-100-nm device structures

John J. Rosato, Yongqiang Lu, Evanson G. Baiya, M. Rao Yalamanchili, and Eric Hansen, SCP Global Technologies

Short product life cycles combined with the transition to 300-nm wafers have been driving the semiconductor industry toward single-wafer processing.¹ The potential advantages of such processing for foundries and pilot lines, for example, include increased product mix flexibility and faster time to first silicon. To date, few facilities have adopted single-wafer tools for wet cleaning and etch steps, primarily owing to their lack of a demonstrated advantage over batch-processing systems. However, as the industry continues its evolution to sub-100-µm technologies—which require more than 100 wet surface-preparation and etch steps—the challenges associated with single-wafer wet processing of devices with high-aspect-ratio features are being addressed.^2,3

Key wet process requirements at the sub-100-nm technology nodes include watermark-free drying, high-efficiency particle cleaning without the wafer damage sometimes caused by high-power megasonics, and oxide etching with angstrom-level control and uniformity. In addition, contamination levels and film loss must be minimized. Compounding these challenges for single-wafer wet processing is the need to reduce process and rinse times to ~30 seconds in order to approach the throughput of batch tools. Short cycle times also are often required to meet the constraints of critical thin-film deposition. The primary roadblock for single-wafer wet processing systems has been the inability to achieve a fast, watermark-free dry. None of the single-wafer tools now on the market can meet this requirement. To address this issue, SCP Global Technologies (Boise, ID) has developed an immersion-based process system that incorporates an isopropyl alcohol (IPA)–vapor condensation drying technology. Another significant feature of the tool is its use of three megasonic transducers. This article describes the system and presents performance data that demonstrate its capabilities in a variety of applications.

Figure 1: Schematic representation of the single-wafer immersion chamber.

Tool Configuration

Figure 1 shows a schematic representation of the Emersion single-wafer immersion chamber. The chamber design includes an array of megasonic transducers, which can be used individually or in various combinations during any process or rinse step, depending on the application. Other features include a specially designed dryer manifold and a fluid-distribution manifold for introducing process chemicals, gases, and DI rinsewater into the chamber. Chemicals can be introduced either in a single-pass, point-of-use fashion or in a recirculating filtered mode to achieve cost savings. All front-end-of-line (FEOL) surface-preparation methods performed in the chamber use conventional process chemicals.

Figure 2: Schematic representation of the two-phase dry approach: (a) the IPA-vapor condensation phase, and (b) the hot N2 final dry during wafer extraction.

The developers of the IPA dry leveraged the company's batch GreenDry system, which has been used successfully in many
sub-100-nm applications.^7,8 Prior to building a prototype system, extensive theoretical modeling was performed to investigate the feasibility of performing an IPA-vapor displacement dry in ~30 seconds, as opposed to the 71/2 minutes required for a 50-wafer batch process.^9,10 This modeling effort led to the concept of a two-stage dry, as depicted in Figure 2. In the vapor condensation phase,
an IPA-vapor cloud is introduced into the chamber using a hot N₂ carrier gas with a relatively low flow rate. This is then followed by a final drying phase during which a very high flow of hot N₂ gas enters the chamber through a knife manifold and impinges upon the wafer while it is being extracted from the chamber at a controlled rate. Modeling results indicated that this two-phase approach was the only way to achieve a dry wafer in the desired 30-second time frame.

Figure 3: Model prediction for total fluid remaining on the wafer surface after a 30-second two-phase dry using various amounts of IPA vapor. Results suggest that injecting 1 ml of IPA vapor is optimal for producing a dry wafer.

Figure 3 depicts the model prediction for a 30-second two-stage dry in terms of the volume of fluid remaining on the wafer after processing with various amounts of IPA vapor. The results indicate that 1 ml is the optimal IPA dispense. If less IPA vapor is injected, there will not be enough surface tension reduction and vapor pressure elevation to remove the residual water from the wafer surface, while injecting larger amounts of IPA vapor will result in too much fluid on the wafer surface, which cannot be evaporated in the 30-second time frame. Based on the modeling results, the two-stage drying process was further optimized on a prototype system.

Experimental validation of the single-wafer drying technology evolved from demonstrating a visual dry to achieving particle neutrality on prime wafers to demonstrating watermark-free performance on device wafers. This validation moved relatively quickly owing to the project team's familiarity with the batch process on which the new technology was based and the insight gained with theoretical modeling.

Figure 4: Particle performance at two threshold levels of the prototype single-wafer system on 300-mm wafers with a 2-mm edge exclusion for several FEOL cleaning sequences over an 18-month period. Comparison of the HF/dry sequence data with the SC-1/HF/dry sequence data highlights the low level of chemical cross-contamination that was achieved.

Particle testing also evolved from demonstrating particle neutrality with a simple rinse/dry process to achieving comparable results with a variety of chemical/rinse/dry sequences, including common FEOL surface-preparation sequences and oxide etches. Figure 4 summarizes particle data for the 300-mm prototype system tested in the company's applications lab over an 18-month period.

Once the process parameters for a particle-neutral dry were established, development work was undertaken with several customers to evaluate the system's watermark performance on a variety of sub-100-nm device wafers. Features on the test wafers included 40:1-aspect-ratio trench structures with philic/phobic interfaces, shallow trench isolation (STI) active areas, and stacked cylindrical capacitors. None of these tests, which included optical, scanning electron microscopy (SEM), and patterned-wafer inspection analyses, revealed the presence of any watermarks.

Figure 5: SEM micrograph of a portion of a 300-mm wafer with 50-nm polysilicon device structures, showing that no stiction-induced bridging had occurred using the IPA-vapor dry.

Figures 5 and 6 show watermark performance results on device wafers with high-aspect-ratio features and sub-100-nm design rules. The customers that participated in this testing had been having problems drying such wafers, especially those processed using HF last steps, during which philic/phobic interfaces tend to trap water. The IPA-vapor technique was found to offer a solution for these surface preparation processes, which are becoming increasingly important for critical film depositions such as ultrathin gate oxides, high-k gate dielectrics, DRAM storage dielectrics, and epitaxial layers.

As with the wafer-drying step, achieving a 30-second cycle time for the cleaning processes run in the single-wafer immersion tool was a critical project goal. This challenge was compounded by the need to use process chemistries that would minimize film loss and reduce surface roughness, as well as the need to keep megasonic power densities low to avoid damaging sensitive device structures. The key factors in cleaning process development thus became the use of an ultradilute SC-1 chemistry (dSC-1 = 1:2:200 NH₄OH:H₂O₂:H₂O) and the incorporation of multiple megasonic transducers in the process chamber. The individual transducers efficiently direct acoustic energy at the wafer surface, and their combined megasonics action allows for the use of low power densities. The transducer configuration also enhances particle removal efficiency via a torque-induced rolling moment acting in concert with multiple wavefronts to multiply the particle lift force.¹¹

Figure 6: Results of performance testing of the IPA-vapor drying step on 300-nm wafers with STI active areas: (a) an optical micrograph, and (b) patterned wafer map and inspection data. Both parts of the figure indicate that there were no watermark patterns on the wafer after drying.

Particle and Metal Removal. In performance testing, particle removal efficiencies of >95% were achieved routinely with aged (>72 hours) Si₃N₄ challenge wafers using various process sequences that included a 30-second dSC-1 step (see Table I). These results demonstrate the benefit of using multiple megasonic transducers in combination to remove particles. The corresponding particle performance results for a dSC-1 clean on prime starting wafers indicated that the cleaned surfaces were consistently particle neutral or negative, as shown in Figure 4, demonstrating that a 30-second process time is also sufficient to clean high-quality incoming wafers.

To ensure ultralow metal-contamination levels, a final metals-cleaning step utilizing a dilute hydrochloric acid (dHCl) single-pass process may be added to any process sequence. Postclean testing has shown that a 30-second process time can be used to meet the metal-level requirements of the latest edition of the roadmap.³ All metal levels tested following an HF/SC-1/dHCl sequence were <2 X 10⁹ cm^–2.

Figure 7: SEM images of 50-nm DRAM storage capacitors following a dSC-1 clean with megasonics: (a) in a batch immersion tool using high power densities, and (b) in the single-wafer chamber with multiple transducers.

Prevention of Wafer Damage and Film Loss. The particle removal results cited above showed that the combined acoustic fields of an array of transducers interact to enhance cleaning efficacy. However, it was equally important to demonstrate that the low (<1 W/cm²) megasonic power densities used in the single-wafer tool can eliminate the risk of damage to device structures that is inherent with the high (>5-W/cm²) power densities utilized in batch tools.

Extensive testing was performed in the single-wafer chamber using test structures that were known to be sensitive to damage when processed in megasonic batch immersion tools. The structures of Figure 7 are stacked cylindrical DRAM storage cells, which are highly vulnerable to lifting and collapsing in megasonic energy fields. Figure 7a shows the damage that was observed following cleaning in a batch immersion tool using standard power densities. It can be clearly seen that the acoustic field intensities were sufficient to damage large regions of the wafer through cavitation effects. In contrast, Figure 7b shows there was no damage to the wafer cleaned in the single-wafer chamber. Patterned-wafer inspection results verified the absence of damage to wafers cleaned in this tool.

As described above, the high-efficiency particle cleaning achieved with the use of multiple megasonic transducers enables the use of an ultradilute SC-1 chemistry and very short process times. Both these factors were found to minimize film loss for oxides, metals, and polysilicon, a capability that is especially important for controlling critical dimensions in sub-100-nm structures. Table II summarizes film losses for two typical cleaning sequences performed in the single-wafer immersion system.

Figure 8: Wafer maps showing oxide etch uniformity for a 20-Å etch on a 300-mm wafer, which had a WIW uniformity of 0.4% (1σ) and a maximum difference across the wafer of only 0.3 Å, and (b) a 10-Å etch on a 200-mm wafer, which had a WIW uniformity of 0.96% (1σ) and a maximum difference across the wafer of only 0.45 Å.

Oxide Etch Processes

Within-Wafer Uniformity. In addition to its wet cleaning capabilities, the single-wafer tool has demonstrated some of the best within-wafer (WIW) etch uniformities ever reported, especially for thin oxide etches.¹² WIW uniformity values of <0.5% (1σ) have been routinely achieved for 20-Å etches on 300-mm wafers, as seen in Figure 8a. On that wafer, the difference between the minimum and maximum values was only 0.3 Å, which is indicative of the excellent fluid dynamics in the process chamber. The wafer map in Figure 8b shows a 10-Å etch on a 200-mm wafer, which had a WIW uniformity of 0.96% (1σ) and a maximum difference across the wafer of only 0.45 Å. Figure 9 summarizes the WIW uniformities for five different etch targets on both 200- and 300-mm wafers. The system's optional use of high-temperature etch processes makes it possible to meet cycle time requirements for thick oxide etches while maintaining excellent etch uniformities.

Figure 9: WIW oxide etch uniformity values (1σ) for various etch targets on 200- and 300-mm wafers. The 230-Å etch uses a high-temperature process.

Wafer-to-Wafer Uniformity. Controlling wafer-to-wafer (WTW) uniformity is particularly challenging for single-wafer systems because it requires that each wafer be exposed to identical process conditions. In addressing this challenge, the immersion tool development team focused first on understanding the oxide etch mechanism in HF chemistry, and then turned to optimizing the chamber design and process parameters to exploit this knowledge.

Although there is general agreement on the thermodynamic aspects of SiO₂ dissolution in HF, understanding of the reaction kinetics and the etch mechanism remains limited.¹³ When the etch rate of thermal SiO₂ films in diluted HF solution (0.5 to 0.05 M, 50:1 to 500:1) was investigated for this project, the results suggested a model with surface chemical reaction–controlled kinetics. It was found experimentally that the fluid dynamics during the etching step have little effect on the etch rate and uniformity, as shown in Table III. However, both the speed and uniformity of rinse quenching are critical factors in controlling the etch uniformity and the etch target.

Based on this understanding, hardware solutions were developed and implemented to obtain quench times of <4 seconds between etch and rinse processes. Figure 10 shows the modeling results for fluid flow in the chamber using a fluid distribution manifold that was optimized to obtain fast, uniform quenching of the etch. Based on the understanding of the etch mechanism and the experiments described above, a control algorithm was developed to improve WTW uniformity. This algorithm takes the etch target as the sole operator input and calculates the required etch time, accounting for the number of wafers processed and the HF concentration and temperature. A 500-wafer marathon run using the algorithm demonstrated that control can be achieved for a 20-Å target SiO₂ etch; as the data shown in Figure 11 reveal, WTW uniformity, or run-to-run repeatability, was <0.4% at 1σ. This uniformity level is believed to be the best reported for any single-wafer wet processor.

Figure 10: Modeling results showing uniform flow distribution across the wafer surface in the process chamber. Average velocity = 23 cm/sec, with σ = 1.3 cm/ sec during rinsing following an HF process.

Chemical Removal. Among the greatest challenges of single-wafer etch processing is to achieve the rapid rinse-up required to avoid chemical cross-contamination of the wafer surface, the chamber wall surfaces, and the chemical recirculation reservoirs. This capability is also needed to meet the goal of 30-second cycle times. The developers of the single-wafer immersion system addressed this problem by designing a process chamber that minimizes fluid volumes and by optimizing the fluid distribution manifolds to achieve very high rinse velocities (see Figure 10). The particle data presented in Figure 4 provide evidence of the lack of chemical cross-contamination, which would result in the formation of Lewis salts that would leave gross particle signatures.

Figure 11: Etch target results for a 500-wafer marathon test with a 20-Å oxide etch. The WTW uniformity value at 1σ was <0.4% and the average WIW value was <0.6%.

Conclusion

A single-wafer immersion processor has been shown to meet the drying, cleaning, and etching requirements of sub-100-nm process technologies. Testing revealed that particle-removal efficiency was high and that there was minimal film loss and no damage from megasonic cleaning of 50-nm structures. The system also exhibited a high level of oxide etch uniformity. In addition, cycle times for the tool can be very short, with process and rinse times of ~30 seconds being typical. This results in cleaning and etching sequences with a total time of ~2 minutes. (In contrast, a typical RCA process performed in a batch immersion tool takes >60 minutes.) The major factors contributing to these capabilities are the cleaning efficiency that is achieved using multiple megasonic transducers and the two-phase IPA-vapor drying process. Furthermore, the use of an optimized fluid-distribution manifold enables fast, uniform rinsing and prevents chemical cross-contamination.

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John J. Rosato, PhD, is a senior process development engineer and executive member of the technical staff at SCP Global Technologies in Boise, ID. He has more than 20 years of experience in the semiconductor industry and has contributed to more than 40 publications. Rosato received an MS and a PhD in electrical engineering from the University of Connecticut in Storrs and a BS in chemical engineering from Tufts University in Boston. (Rosato can be reached at 208/685-3236 or jrosato@scpglobal.com.)

 

 

Yongqiang Lu, PhD, is a senior process development engineer in the R&D department at SCP Global Technologies. Before joining the company, he worked for Lucent Technologies and MEMC. Lu has authored more than 20 publications. He received a PhD in metallurgical engineering from the University of Utah in Salt Lake City. (Lu can be reached at 208/685-3277 or ylu@scpglobal.com.)

 

 

Evanson G. Baiya is a process development engineer at SCP Global Technologies where his research focus is on the effect of wafer cleans on semiconductor device performance. He received a BS in chemistry from Idaho State University in Pocatello. (Baiya can be reached at 208/685-4066 or ebaiya@scpglobal.com.)

 

 

M. Rao Yalamanchili, PhD, is director of the process R&D group at SCP Global Technologies. He has authored more than 50 publications in peer-reviewed journals and proceedings in the areas of particle interactions and surface contamination. He received a PhD in metallurgical engineering from the University of Utah in Salt Lake City. (Yalamanchili can be reached at 208/685-4053 or ryalamanchili@scpglobal.com.)

 

 

Eric Hansen is CTO of SCP Global Technologies and is responsible for development of emerging technologies. He joined the company in 1981 and has held positions in engineering, engineering management, and senior management. He received a BS in electrical engineering from Washington State University in Pullman. (Hansen can be reached at 208/685-3246 or ehansen@scpglobal.com.)

Process Sequence Particle Removal Efficiency (%)