The chart divides processes into their FEOL and BEOL constituents. Tews says the team separated FEOL processing into "building blocks" beginning with shallow-trench isolation, shown as segment one. Typically, each block consists of a lithography step, an implantation step, cleans, and strips, he says. The number of implant levels depends on the number of different types of transistors on the chip. Contact holes, shown as number nine, mark the transition between FEOL and BEOL, notes Tews, adding "for many products BEOL is more expensive than FEOL."

Regarding production costs, Tews says chipmakers try to minimize the use of metal levels because they require very expensive lithography. A device manufacturer will switch to 2X metals—meaning the width of the metal layers is twice as large as 1X metals—as soon as possible. For the sake of their cost calculations, Tews and crew assumed two metal levels with 2X metals. Determining the number of 1, 2, and 4X levels requires striking a difficult balance between area request and processing costs, Tews says.

The winning wafer technology will need to be available when the industry is ready to jump to the next process node. The market ultimately will determine which device concepts and wafer types will emerge to keep the industry on the schedule dictated by the ITRS, the Infineon team concludes.