Reducing defects in integrated surface-micromachined accelerometers

David E. Grosjean, Analog Devices

Volume MEMS fabrication involves unique yield-loss mechanisms, but its defect reduction and yield enhancement techniques are often the same as those used in the manufacture of traditional integrated circuits. As in standard IC fabs, MEMS fabs are concerned with yield models, defect densities, fault detection, and defect reduction to enhance yields and improve device quality. Defect reduction efforts at Analog Devices (Cambridge, MA) play a dual role in the integrated MEMS (iMEMS) process used to fabricate integrated accelerometers. Because the process combines MEMS structures and BiCMOS circuitry on a single chip, defect reduction efforts can improve the MEMS devices as well as the device circuitry. This article discusses iMEMS yield-loss mechanisms and outlines how reducing the incidence of masking defects generated during photolithography substantially improves both sensor- and circuitry-related yields on accelerometer chips.

Integrated Accelerometers

The iMEMS acceler-ometer is primarily used as a crash sensor in air-bag deployment modules for automobiles. The sensor is composed of a single layer of suspended structural polysilicon from which a movable proof mass and fixed interdigitated fingers for capacitive sensing are formed. Figure 1a presents a schematic diagram of the accelerometer's sensor operation during applied acceleration, and Figure 1b shows an SEM micrograph image of an actual silicon device. Although the proof mass is anchored to the substrate, it is allowed to move through folded tethers. When the sensor experiences an acceleration in its sensing plane, the proof mass moves, and a difference in capacitance between the fixed fingers is measured (ΔC = C – C´ in Figure 1a). (When no acceleration occurs, ΔC = 0.) The difference in capacitance is then converted to a dc output proportional to the acceleration. The functioning of the accelerometer is described in greater detail elsewhere.^1,2

Figure 1: Schematic diagram of (a) an accelerometer's sensor operation during applied acceleration, and (b) an SEM micrograph image of an actual silicon device.

Because the accelerometer's primary function is to ensure automobile safety, it must be a high-quality device that is both reliable and inexpensive. In other words, die sizes must be reduced from product generation to product generation and yields must be maximized. Since 1993, when Analog Devices began the shipment of more than 100 million such devices, most systematic yield-loss problems have been solved, allowing the company's micromachined products division to focus on reducing the incidence of random defects. Successful efforts to reduce random defects have been encouraged by the company's customers, who demand single-digit parts-per-million failure rates.

MEMS Sensor-Circuit Integration Methods

There are several methods for integrating a surface-micromachined MEMS sensor with the circuitry necessary to measure acceleration and then output an electrical signal proportional to the magnitude of the acceleration. Two separate chips, one with a sensor and one with CMOS circuitry, can be made. Such chips can then be wirebonded together, bonded together in a flip-chip style, or even wafer bonded together before dicing. In such cases, separate defect reduction measures, most likely performed in different fabs, would be required for each process.

For performance and cost reasons, however, it is preferable to combine the sensor and circuitry on the same wafer. There are several ways to achieve such integration. Either the MEMS device can be fabricated first, followed by the circuitry (MEMS first), or the circuitry can be fabricated first, followed by the MEMS device (MEMS last).

Both methods pose different processing challenges. For example, in a MEMS-first process developed by Sandia National Laboratories (Albuquerque), MEMS devices are placed in a trench and then buried in oxide, after which the whole wafer is planarized and annealed in preparation for the CMOS circuitry.³ While such processing prevents temperature-induced damage to the CMOS circuitry, it can cause topography problems. In MEMS-last processing, the high temperatures of polysilicon deposition can melt aluminum interconnects. To avoid that problem, Texas Instruments (Dallas) developed a low-temperature surface micromachining process for its Digital Micromirror Device.⁴ In contrast, a group at the University of California, Berkeley, replaced aluminum with tungsten, which can withstand high processing temperatures.⁵

In the iMEMS process, the MEMS sensor is actually fabricated within a mature BiCMOS process.^6,7 First, all BiCMOS circuitry is created through the poly gates, leaving an empty area in the center of the die for the sensor. Second, the MEMS sensor element is created by depositing a 1.6-µm-thick sacrificial oxide (sacox) layer followed by a 2–4-µm thick polysilicon layer. Then the sensor is patterned. Third, aluminum interconnects are formed and the device is passivated. Fourth, the sensor is released while the circuit remains protected. By fabricating the sensor before forming the interconnects, the aluminum interconnects will not melt. Furthermore, the BiCMOS process, with its deep junctions, is resistant to the extra depositions and anneals associated with the MEMS sensor fabrication.

How Photo Defects Affect Accelerometer Functionality

Regardless of how MEMS devices and circuitry are integrated, each processing method generates particular defects. To detect and classify defects on sample wafers, Analog Devices employs a line-partitioning inspection methodology similar to that used by most IC manufacturers. At several important steps in the fabrication process, a production lot sample is chosen for automated inspection using a KLA 2132 patterned-wafer inspection tool from KLA-Tencor (San Jose) and an INS2000 off-line inspection microscope from Leica (Solms, Germany). Defect data are analyzed and trended, and the results are fed back to the process engineers when problems are found. The data are also used by an active fab defect reduction team to seek longer-term solutions to problems.

Defects that prevent the proof mass in the accelerometer from moving are of particular concern. At probe, one test deflects the proof mass with an applied bias and measures the capacitance change in order to simulate an applied acceleration. Any defect that impedes that motion, such as a particle, residue, or photo-track-induced masking defect, can cause the die to fail at probe.

Figure 2: Photo-track-induced defect spot of sensor poly that was not etched away, holding a point on the tether that was supposed to be movable.

If a photo-track-induced defect prevents a portion of the sensor from being etched, the motion of the proof mass can be hindered. Photo-track-induced defects capable of masking etch processes can be caused by particles in the resist and residues from the resist, solvent, or developer left behind as a result of fluctuations in the track exhaust; by bubbles in the developer dispense; or by incomplete postdevelop rinsing. Figure 2 illustrates a spot of sensor poly that was not etched away, holding a point on the tether that was supposed to be movable. If a spot of that size is present somewhere on the fingers, as in Figure 3, the proof mass cannot move. A more serious problem arises when the sensor's two capacitors are shorted together. At probe, that type of failure is indistinguishable from a short in the circuit's metal lines.

Figure 3: Photo-track-induced defect caused during the sensor etch step. Such a spot present on the fingers prevents the proof mass from moving, leading to capacitor shorts.

Because contacts and metal lines are formed after the sensor is created, defects generated during sensor processing can affect the circuit. In Figure 4, a spot of residue is shown blocking a contact between aluminum and poly interconnects, resulting in a circuit open. A more subtle problem is shown in Figure 5, where a spot of the sensor poly/sacox stack left in the circuit area formed a mesa. The 1-µm-thick aluminum interconnect covered a step height of about 3.6 µm (a 1.6-µm sacox and a 2-µm sensor poly). Although not particularly severe, such a defect can cause an open or short circuit at probe if metal residue is left along the sides of the mesa.

Figure 4: A spot of residue blocking a contact between aluminum and poly interconnects, resulting in a circuit open.

Any photo-track-induced defects created at the metal layer can cause shorts in adjacent interconnects. But what if aluminum spots remain over the sensor area? During the metal deposition step in the iMEMS process, the sensor is protected by an oxide/nitride stack. If metal residue remains over the sensor area, it is removed when the sensor is opened and subsequently released in a long hydrofluoric acid dip. Thus, there is no danger of metal spots bridging sensor fingers.

Using Improved Photolithography Tracks to Lower Defect Levels

The micromachined products division at Analog Devices originally used coater/developer tracks based on an older technology that prevented further defect reduction gains. When additional tracks were required to meet production goals, the Mark VII from TEL (Austin, TX) was chosen because of its high throughput, small footprint, low cost, and advanced technology. The track's improved edge bead removal (EBR) nozzle design reduces splashing or spitting during EBR solvent dispense, while its exhaust control mechanism reduces photo defects by diverting splashed fluid away from the wafer surface. Finally, its dispense function is much less turbulent than that of the older track, dispensing developer more uniformly over the wafer surface and greatly reducing bubbles that can lead to micromasking defects. The TEL track monitors the flow of developer and DI water, and sounds an alarm when inadequate and unrepeatable rinse conditions exist.

Figure 5: Examples of a spot of the sensor poly/sacrificial oxide stack left in the circuit area, which caused the formation of a mesa.

To determine whether the use of the new tracks resulted in lower photo spot defect densities than the old tracks, split lot experiments were run at each of the four critical layers (thermal oxide, gate poly, sensor poly, and metal) and then inspected using the KLA 2132 and the INS2000 microscope. As illustrated in Figure 6 for a single lot and critical layer, five wafers were coated and developed on the old tracks, five were coated on the new tracks and developed on the old tracks, five were coated on the old tracks and developed on the new tracks, and five were coated and developed on the new tracks. All other photo steps in the process were performed on the old tracks alone. Two lots at each critical layer were run using this procedure (for a total of eight lots), demonstrating the defect impact of both the old and new tracks.

Figure 6: Schematic diagram illustrating how a 20-wafer lot was split, processed, and inspected.

The results from that part of the test are shown in Figure 7, which presents average photo defect densities on three critical layers as a function of which combination of tracks performed the coating and developing steps. The bars in the chart represent one standard deviation in the data. These data revealed that the use of the new tracks resulted in >50% fewer defects than the use of the old tracks.

Figure 7: Average photo defect densities on (a) poly, (b) sensor, and (c) metal layers as a function of which combination of tracks performed the coating and developing steps.

The next step in the test involved the measurement of yield improvement at probe. Because each critical layer was qualified and released before the next layer was processed, the investigators were able to measure the cumulative effects of using the new tracks. Figure 8 plots the parametric yield loss resulting from such circuit problems at probe as opens and shorts (including shorts across the sensor fingers) as a function of the number of critical layers that were processed in the new tracks. (Such circuit problems are primarily caused by photo-track defects.) Since the data were generated from only one product type, critical areas were identical between wafers. Each bar (data point) represents at least 1500 processed wafers. Processing all four critical layers in the new tracks resulted in approximately 50% less defect-related yield loss than processing them in the old tracks.

Figure 8: Data illustrating parametric yield loss at probe from such circuit problems as opens and shorts as a function of the number of critical layers processed in the new tracks.

MEMS Yield Modeling

The nature of the work discussed in this article and the types of data that were collected lead naturally to a probe yield model based on a partitioning methodology.^8,9 The total yield at probe can be written as

Y = Y_S Y_D

where Y_S is the systematic yield and Y_D is the defect-limited yield. Breaking down the defect-limited yield into defect-source components results in

where Y_n is the yield loss for a particular defect type (but only in high-yield processes). In the above equation, yield resulting from photo-track defects is expressed as Y_photo. The Poisson yield model is a good approximation of the yield for the small dies fabricated at Analog Devices and can be applied to each defect type:

Y_n = exp^–D_0,n^A

where D_0,n is the defect density of an nth defect type and A is the defect-sensitive area. Because a possible interaction between layers (i.e., sensor poly and metal) is not a serious problem for a data set involving 2-µm sensor poly layers, it has been ignored here. Using the

Figure 9: Photo-track defect densities on wafers processed (a) during a five-month period on the old tracks, and (b) during a four-month period on the new tracks.

above equations and assuming that all other defect mechanisms and systematic yield mechanisms remained unchanged, a comparison between the probe yield before and after the full implementation of the new tracks results in

To conclude the test, the investigators determined that the implementation of the new track resulted in a large improvement in photo-track defect densities, as summarized in Figure 9. Figure 10 shows the improvement in overall yield at probe as a function of the number of critical layers that were processed in the new tracks. An evaluation of the final equation, with Y_TEL equaling the yield value of the four critical layers in Figure 10, Y_old equaling the yield value of zero critical layers in Figure 10, and the D₀s being derived from Figure 9, demonstrates that the MEMS yield model can predict measured yield improvement at probe to within 0.2 percentage point.

Figure 10: Improvement in overall yield at probe as a function of the number of critical layers processed in the new tracks.

Conclusion

This article describes yield-loss mechanisms in Analog Devices' iMEMS process and demonstrates how yield enhancement measures can improve the yields of both the MEMS sensor and the BiCMOS circuitry. After testing old and new tracks to coat and develop four critical layers, the investigators determined that the new system resulted in >50% less defect-related yield loss than the old system, and substantially less overall yield loss at probe. Using a simple Poisson yield model with partitioning, they verified that the measured improvement in photo-track-induced defect densities led to a yield improvement at probe.

Acknowledgments

The author gratefully acknowledges the assistance of Jody Keller for collecting data, photographing defects, and performing numerous other tasks. He would also like to thank Terry Egan and Barbara Berthold for collecting data, Ian Fink for his extensive work on the photo tracks, Bill O'Mara and David Kneedler for reviewing the manuscript, and Craig Core and Michelle Farrington for their encouragement.

References

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David E. Grosjean, PhD, is a staff yield engineer in the micromachined products division of Analog Devices (Cambridge, MA), where he is responsible for enhancing yield and reducing defects throughout the manufacturing process. Before joining the company in 1999, he was an NSF-CGP postdoctoral fellow at NEC in Tsukuba, Japan, researching electromigration in aluminum/copper interconnects. He is a member of the Materials Research Society, IEEE, and Tau Beta Pi. He received a BS in applied math from Yale University in New Haven, CT, and a PhD in engineering physics from the University of Virginia in Charlottesville. (Grosjean can be reached at 617/761-7123 or david.grosjean@analog.com.)