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MicroMagazine.com

Using simulation-based technology to qualify altPSM for 193-nm lithography

Yasutaka Morikawa and Naoya Hayashi, Dainippon Printing; and
Linyong Pang and Gerard T. Luk-Pat, Numerical Technologies

Defect printability experiments have validated the suitability of a software-based simulation system for next-generation semiconductor applications.

Fabricating subwavelength devices within the 130-nm and smaller technology nodes specified in The International Technology Roadmap for Semiconductors presents many challenges.1 The combination of continually increasing circuit densities and ever-smaller features has especially affected photomask manufacturing. Once considered mere commodities, masks have evolved to become a key enabling technology for next-generation production.

While the industry continues to extend photolithography's capabilities through resolution-enhancement techniques such as optical proximity correction and phase-shift masks, the use of alternating-aperture phase-shift mask (altPSM) technology to meet future-generation needs has attracted much interest.2 The use of altPSMs has already extended 248-nm-wavelength lithographic performance into the low-k dielectric regime at the 130- and 100-nm technology nodes. ICs are now being produced with 0.13- and 0.10-µm design rules, incorporating transistor gate sizes of 65 nm, or just one-third the actinic wavelength, and altPSM technology has proved to be the most effective solution for these process generations.1 Its most important benefit is the excellent control of critical dimensions that results from both the large depth of focus and favorably low mask-error enhancement factor values of ~0.5, which have been demonstrated through pitch and defocus experiments.3

Given the semiconductor industry's sensitivities to costs, many mask makers and users also have recently adopted simulation-based photomask defect qualification. Such technologies can prevent the performance of unnecessary mask repairs, reduce the need for review steps, and ensure consistent communications between suppliers and users, thus reducing turnaround times and overall mask-related expenditures. Simulation techniques have been validated for both binary and attenuated phase-shift masks (attPSMs), delivering accurate results across multiple defect types independent of the inspection tool's wavelength.4 The wealth of experimental data and production results amassed over the past 2 years have established that this method of characterizing mask defects is a mature, reliable solution for such masks.5–14 With the industry now ready to reap the benefits of altPSM, it is imperative that simulation-based technology be successfully extended for use with these advanced photomasks in 193-nm-wavelength production.

Results of simulation experiments on altPSM masks using a 248-nm krypton fluoride (KrF) stepper have been promising, showing good correlation between simulated and printed images for all three types of advanced photomasks.15,16 Expanding on that previous work, this article presents the results of a collaborative simulation-based defect printability study performed on altPSMs designed for 193-nm lithography. The study used masks fabricated by Dainippon Printing (DNP; Saitama, Japan) with programmed defects of known size, phase, and location. Wafer prints were simulated from these masks using the Virtual Stepper system from Numerical Technologies (San Jose), which takes inspection images as input and models the lithography process.

Mask Defect Qualification Challenges

In the past, mask defects were classified as either clear or opaque, but as subwavelength lithography and resolution-enhancement methods have become more prevalent, so too has the importance of "shades of gray" defects. Besides unwanted (opaque) and missing (clear) chrome, defects may be particles, minute fissures or polishing grooves in the quartz layer, scratches, and partially transparent films. They also may involve nonuniform transmission of light through the pellicle, electrostatic discharges, transmission capability loss, subpellicle crystal growth, and other factors.

Device feature line-edge roughness further complicates how these defects should be handled. Since most critical dimension (CD) measurements are made using optical systems with limited resolution, line-edge roughness causes the results to have a higher degree of uncertainty than the tolerances generally specified by mask users.

Because the inspection systems flag many defects that may not print during the lithography process, it is important to accurately correlate the defects detected on the mask with the matching areas on a printed wafer. Any defects that do not print can be considered nuisance defects; fixing them is not only time-consuming, expensive, and prone to error, it also is often unnecessary. Simulation-based defect characterization techniques enable the photomask industry to quantify the effects of nuisance defects by providing an accurate visualization of the images that will be produced on the silicon substrate using a given mask and specific lithographic process. These capabilities offer a reliable set of data that can be used to make decisions regarding the mask's usability quickly and automatically, and thus eliminate the costs associated with repairing nuisance defects.

Four characteristics—shape, size, transmission, and phase—determine the severity of the defects mentioned above. Of these, the effects of the first three are known and have been studied in great detail.4–14 But the fourth is still a concern. How a defect prints is highly dependent on how widely the phase angle differs from the specification, but the ability of inspection to transfer phase information is limited. Also, because phase defects are harder to repair than other defect types, accurately predicting their printability is important to both mask houses and fabs.

The ability to detect and disposition phase defects will continue to increase in difficulty with each technology node. For 193-nm lithography, which uses an argon fluoride (ArF) laser rather than the KrF laser used at 248 nm, the trench depth of etched quartz altPSM structures will decrease from 244 to 171 nm.17 A 60° phase defect with KrF would have a depth of 81 nm, which can be easily detected by current inspection systems, but because a 60° phase defect using ArF would have a depth of only 57 nm, it would be extremely difficult to detect and characterize.

Because extracting accurate phase information from mask- inspection systems is proving to be very difficult, not to say impossible, the industry has been exploring other types of metrology equipment. Tools have become available that provide direct measurements from which phase data can be inferred. For example, an atomic force microscope can provide a specific profile of a microscopic defect, from which the phase of the defect can be calculated. Interferometer-based systems can yield data on the phase of a structure on an altPSM, but correctly extracting the phase information of a defect within that structure is exponentially more difficult.

These alternatives are very localized in application and are too time-consuming, expensive, and impractical for use in production. A viable solution is to enhance the capabilities of mature simulation-based mask qualification techniques by incorporating new algorithms and assumptions based on prior intelligence, and use the simulation results to disposition advanced mask defects without the need for specific phase information.

Figure 1: Cross section of an altPSM structure showing the single trench with undercut.

To verify the efficacy of this approach, test masks were fabricated with programmed phase defects that ranged in size from 20 to 400 nm and had a phase angle of 25°, 50°, or 75°. Line-and-space and dense-rectangle patterns were included. Defect detectability was tested using an SLF27 inspection system from KLA-Tencor (San Jose), while images were acquired using the SLF27 and an MD3000 inspection system from Lasertec (Yokohama, Japan). Defect dispositioning was investigated using actual wafer prints and simulations from the hardware-based MSM193 Aerial Image Measurement System (AIMS) from Karl Zeiss (Thornwood, NY) and from the software-based Virtual Stepper system. CD data from the wafer prints and the two simulations were compared.

Test Mask Fabrication

Fabricated by a two-step process in which dry etching is followed by wet etching, DNP's standard altPSM structure, shown in Figure 1, is etched quartz with a single undercut trench. Targeting the depth of each step helps control the undercut. For ArF and altPSM lithography, the standard dry etching depth is 71 nm, which corresponds to 75°, and the wet etching depth is 100 nm, which corresponds to 105°. In comparison, for KrF and altPSM lithography, the dry etching depths are 94 nm and the wet etching depths are 150 nm, which correspond to 65° and 115°, respectively.

This two-step etching process can affect the 3-D shape of a defect. For example, a bump defect caused by dry etching will be altered by the subsequent wet etch, but a dry-etch trench defect in a 0°-phase region will not be exposed to the wet etch. Furthermore, dry etching is more likely than wet etching to create defects, because most etch-related defects are caused by small particles. Particles present at the start of dry etching, such as resist residues or contaminants from the etch chamber, are likely to become phase defects. However, particles present at the start of wet etching probably will not become defects because the wet etching solution can easily penetrate between them and the quartz. The study described here focused on dry-etching defects.

Figure 2: The Type-A pattern design (a) and examples of the four defect categories included in this pattern: (b) an edge trench and edge bump, and (c) an isolation trench and isolation bump.
Figure 3: The Type-B pattern design (a) and examples of the four defect categories included in this pattern: (b) an edge trench and edge bump, and (c) an isolation trench and isolation bump.

The 193-nm ArF test masks created for this study have a reticle-to-wafer magnification of 4X and feature a single-trench altPSM structure with a 100-nm undercut and a 100-nm-node basic cell design. The two patterns used on the masks are shown in Figures 2 and 3, along with diagrams depicting examples of the four defect categories—edge bump, isolated bump, edge trench, and isolated trench—that are included in both designs. At 1X, the Type-A pattern, a dense rectangle, has a 150-nm half-pitch and 80-nm gate; a line CD of 80 nm; x, y pitches of 300 and 800 nm, respectively; and x, y openings of 220 and 615 nm, respectively. At the same magnification, the Type-B line-and-space pattern has a 100-nm half-pitch and 100-nm line, a line CD of 100 nm, an x pitch of 200 nm, and an x space of 100 nm. There were 16 defect sizes ranging from 20 to 400 nm at 4X.

The regular mask was fabricated with the following process:

* Posi-type chemically amplified resist was applied to the AR/chrome layer and 6025 quartz substrate of blank masks.

* A 50-kV electron beam was used to perform chrome dry etching.

* A 50-kV electron beam was used to perform the shifter process (quartz dry and wet etching).

Three phases (25°, 50°, and 75°) were fabricated separately using dry etching. Phase values were measured using the Lasertec MPM193 phase-shift mask measurement system. All 75°-phase defect regions were captured by a KLA-Tencor 8100 XP-R critical-dimension scanning electron microscope (CD-SEM). Figure 4 shows measured defect size as a function of programmed defect size—with size defined as the square root of the defect area—for both patterns. The two graphs illustrate why trench-defect resolution was limited to 120 nm. Bump-defect resolution was better because these defects are wet and dry etched.

Figure 4: Measured defect size versus programmed defect size (a) for Type-A pattern results, and (b) for Type-B pattern results. Size is defined in this case as the square root of the defect area.

Experimental Conditions and Results

Defect Detectability. The test masks were inspected with the SLF27 system using the instrument's die-to-die and Starlight modes, and a pixel size of 150 nm. The results from these inspections were correlated with the AIMS images. Transmitted- and reflected-light approaches were used for die-to-die inspections. Defects shallower than 75° could not be detected by transmitted light. For example, Figure 5 shows the defect design and images for a 75° edge-bump defect with a measured size of 371 nm on a Type-A pattern. The defect can be identified easily in the reflected-light image, but not in the transmitted-light image. Because this defect was one of the largest in the study, reflected-light inspection was deemed necessary to detect phase defects.

Figure 5: The design and images of a 75° edge-bump defect on a Type-A pattern: (a) defect design, (b) SEM image, (c) transmitted-light image, and (d) reflected-light image.

The 25° defects were not detectable with either the die-to-die reflected-light mode or Starlight mode, although it was noted that the latter mode was more sensitive than the former. Also, all defects with a specified AIMS printed-CD change of ±10% or greater were detected successfully.

Printability. Using positive resist and 193-nm lithography, actual wafers were printed with defects from two categories: edge bump and edge trench. These results were compared with results from the AIMS. The following scanner and AIMS parameters were used: a reduction ratio of 1:4, a numerical aperture of 0.7, and an illumination sigma of 0.4.

The 8100XP-R CD-SEM was used to measure line CDs on the printed and developed resist images for both defect and reference areas. Although large amounts of visual data and charts were generated during this phase of the study, for reasons of space Figure 6 only depicts details of the results for a 75° edge-bump defect on a Type-A pattern. Figure 6a shows the ratio of defect CD to reference CD versus depth of focus (DOF), as measured using an SEM image. Figure 6b is the comparable AIMS result for this defect. As the figure indicates, there was good basic agreement between the wafer prints and the AIMS results, but the consistency of the AIMS data made it easier to recognize the tendency of the defects to print.

Figure 6: Example of printability results for a 75° edge-bump defect on a Type-A pattern: (a) the ratio of defect CD to reference CD as a function of focus error as measured on an SEM image of a printed wafer, and (b) the corresponding AIMS simulation data. The green boxes represent ±10% CD variations and ±0.10-µm focus variations.

To generalize, it was found that phase defects smaller than 400 nm and shallower than 25° did not cause 10% CD errors at DOF that were accurate within ±0.10 µm. For both patterns, larger defects produced larger CD errors, as expected. For the Type-A pattern, CD accuracy depended strongly on defect size as the focus error increased, while for the Type-B pattern, CD changes were less dependent on DOF.

Lithography Simulation. In the next phase of the study, wafer prints from the test masks were simulated using the Virtual Stepper system. While this simulation-based mask-defect characterization system has been validated with binary masks and attPSMs, its use with altPSMs requires morecareful reconstruction of the mask from inspection images. Obstacles to mask reconstruction include the lack of explicit phase information, quantization noise, and blurring by the inspection system. Phase defects may be recognized by interference between transparent defects and transparent nondefects, as illustrated in Figure 7. The images in the figure are subtractions of test and reference images from an SLF27 system for a Type-A pattern with a programmed defect size of 400 nm and phase of 75°. Because the bump defects are on otherwise 180° areas, the phase of their defect areas is 105°. Similarly, because the trench defects are on otherwise 0° areas, the phase of their defect areas is 75°.

Figure 7: Interference effects of different defects: (a) a left-edge bump, (b) an isolated bump, (c) a right-edge trench, and (d) an isolated trench. The green boxes show the reconstructed defect areas.

The SLF27 uses a wavelength of 365 nm and a mask pixel size of 150 nm; the MD3000 uses a 248-nm wavelength and 62.5-nm pixels. Complex-valued fields were reconstructed using the amplitude-only images from these systems, and wafer prints were simulated from these data using the Virtual Stepper. The CD near each defect was measured on each simulated print by drawing two cutlines: the so-called defect cutline was drawn near the defect and the reference cutline was drawn on a similar feature away from the defect. Next, the resist process was modeled with a single threshold, using the reference cutline to determine the intensity level that would yield the target CD. This intensity level was then used to measure the CD on the defect cutline. The CDs of interest were also measured on wafer prints and on the corresponding AIMS images using a similar procedure. (The AIMS uses a wavelength of 193 nm and a pixel size of 81.5 nm.)

Figures 8 and 9 show inspection and simulation images for 400-nm, 75° edge-bump and isolated-trench defects. The MD3000 images are sharper than the SLF27 images because of the former's shorter inspection wavelength.

Figure 8: Inspection images and simulated wafer prints for a 75°, 400-nm edge-bump defect on a Type-B pattern: (a) SLF27 inspection image, (b) MD3000 inspection image, (c) stepper simulation, and (d) AIMS simulation. In (a) and (b), the red boxes indicate defect areas; in (c) and (d), the blue lines are the reference cutlines and the red lines are the defect cutlines.
Figure 9: Inspection images and simulated wafer prints for a 75°, 400-nm isolated-trench defect on a Type-A pattern: (a) SLF27 inspection image, (b) MD3000 inspection image, (c) stepper simulation, and (d) AIMS simulation. In (a) and (b), the red boxes indicate the defect areas; in (c) and (d), the blue lines are the reference cutlines and the red lines are the defect cutlines.

Figure 10 summarizes the results for Type-B line-and-space patterns with 100-nm target CDs and 75° defects from all four categories. The Virtual Stepper–simulated images derived from both the SLF27 and MD3000 were in good agreement with the AIMS measurements and wafer prints. For all four types of defects, the average difference between the SLF27-derived stepper simulation images and AIMS results was 1.3%, while the average difference between the stepper simulations and the wafer prints was 3.9%. And for all four types of defects, the average difference between the MD3000-derived stepper simulation images and AIMS results was 3.4%, while the average difference between the stepper simulation and the wafer prints was 2.3%. The results from the tests performed with the SLF27 differ slightly from those from the MD3000 because the two systems use different wavelengths.

Figure 10: Comparison between CD measurements for a Type-B pattern from SLF27- and MD3000-derived Virtual Stepper simulations, AIMS simulations, and wafer prints. Programmed defect sizes are on the mask scale, while the CDs are on the wafer scale, which is one-quarter of the mask scale.

Stepper simulations derived from SLF27 images of Type-A patterns with 80-nm target CD measurements were also studied, and the CD measurements for 50° and 75° defects were compared. Among all the images, variations in cutline position with respect to the defect position and the host pattern were found. From these variations, it was estimated that the maximum CD error was 2 nm.

Conclusion

The challenges of subwavelength lithography present new opportunities for the photomask industry, since advanced masks are enablers for next-generation semiconductor manufacturing. Simulation-based mask qualification is an important contributor to that transition. It has been used successfully with binary masks, attPSMs and altPSMs to eliminate unnecessary repairs of nuisance defects, minimize the need for review resources, and ensure consistent communications between mask suppliers and users.

This study, which used new algorithms for simulating altPSM phase defects with 193-nm lithography, validated the applicability of simulation-based mask qualification for the next generation of process technologies. CD measurements from a Virtual Stepper were shown to be in close agreement with those from AIMS and wafer print SEM images. The stepper simulation technology is available for use with all advanced photomasks, and research has indicated that it could complement defect-measurement equipment from suppliers such as KLA-Tencor and Actinix.18,19 To achieve industrywide agreement on its terminology and application, simulation is an active agenda item within the SEMI task force on photomask qualification terminology.20 The technology is limited only by the information that can be provided by semiconductor equipment. As new inspection tools (e.g., AFMs) are developed, simulation-based mask-qualification systems will have access to additional data, such as direct phase information.

Acknowledgments

This article is a revised version of a paper presented at the BACUS Symposium on Photomask Technology held September 30–October 4, 2002, in Monterey, CA. The authors would like to thank Yoshio Tanaka, J. Tracy Weed, Fang-Cheng Chang, and David Pinto from Numerical Technologies for their valuable input.

References

1. The International Technology Roadmap for Semiconductors (San Jose: Semiconductor Industry Association, 2001); available from Internet: http:// public.itrs.net.

2. M Levenson, N Viswanathan, and R Simpson, "Improving Resolution in Photolithography with a Phase-Shifting Mask," IEEE Transactions on Electron Devices 29 (1982): 1828–1836.

3. G Vandenberghe et al., "Performance Optimization of the Double-Exposure Alternating PSM for (Sub-)100-nm ICs," in Proceedings of SPIE, 21st Annual BACUS Symposium on Photomask Technology, vol. 4562 (Bellingham, WA: SPIE, 2001), 394–405.

4. SY Chiou et al., "Implementing Simulation-Based Mask-Qualification Technology," MICRO 20, no. 2 (2002): 29–38.

5. C Tinaztepe and I Kagami, "Simulation-Based Defect Printability Analysis for 0.13-µm Technology," in Proceedings of SPIE, Photomask and Next-Generation Lithography Mask Technology VIII, vol. 4409 (Bellingham, WA: SPIE, 2001), 518–519.

6. ER Poortinga et al., "Comparing Software and Hardware Simulation Tools on an Embedded-Attenuated PSM," MICRO 18, no. 6 (2000): 69–91.

7. I Kagami, "A Study on Photomask Defect Printability and Quality Assurance for 0.13 Micron Technology" (paper presented at the Yield Management Seminar, Makuhari, Japan, December 2000).

8. K Phan et al., "Comparison of Binary Mask Defect Printability Analysis Using Virtual Stepper System and Aerial Image Microscope System," in Proceedings of SPIE, 19th Annual Symposium on Photomask Technology, vol. 3873 (Bellingham, WA: SPIE, 1999), 681–693.

9. D Pettibone et al., "Wafer Printability Simulation Accuracy Based on UV Optical Inspection Images of Reticle Defects," in Proceedings of SPIE, Metrology, Inspection, and Process Control for Microlithography XIII, vol. 3677 (Bellingham, WA: SPIE, 1999), 711–721.

10. L Karklin and S Mazor, "Photomask Quality Control by Virtual Stepper System for Subwavelength Photomasks," in Proceedings of SPIE, Photomask and Next-Generation Lithography Mask Technology VIII, vol. 4409 (Bellingham, WA: SPIE, 2001), 512–517.

11. Y Maenaka et al., "Defect Printability Analysis of Attenuated PSM Using PASS," in Proceedings of SPIE, 21st Annual BACUS Symposium on Photomask Technology, vol. 4562 (Bellingham, WA: SPIE, 2002), 468–479.

12. "Virtual Stepper System Reference Manual," version 2.1 (San Jose: Numerical Technologies, 2001).

13. J Novak et al., "Defect Dispositioning Using Mask Printability on Attenuated Phase-Shift Production Photomasks," in Proceedings of SPIE, Photomask and Next-Generation Lithography Mask Technology VIII, vol. 4409 (Bellingham, WA: SPIE, 2001), 488–498.

14. L Pang et al., "Simulation Based Defect Printability Analysis on Attenuated Phase-Shifting Masks," in Proceedings of SPIE, Photomask and Next-Generation Lithography Mask Technology IX, vol. 4754 (Bellingham, WA: SPIE, 2002), 651–658.

15. L Pang et al, "Defect Printability Analysis on Alternating Phase-Shifting Masks," in Proceedings of SPIE, Photomask and Next-Generation Lithography Mask Technology IX, vol. 4754 (Bellingham, WA: SPIE, 2002), 613–620.

16. CH Chang et al., "Defect Dispositioning Using Mask Printability Analysis on Alternating Phase-Shifting Masks," in Proceedings of SPIE, Photomask and Next-Generation Lithography Mask Technology IX, vol. 4754 (Bellingham, WA: SPIE, 2002), 621–628.

17. Y Morikawa et al., "Study of Defect Printability Analysis on Alternating Phase-Shifting Masks for 193-nm Lithography," in Proceedings of SPIE, 22nd Annual BACUS Symposium on Photomask Technology, vol. 4889 (Bellingham, WA: SPIE, 2002), in press.

18. LS Zurbrick et al., "Alternating Phase-Shift Mask Inspection through the Use of Phase-Contrast Enhancement Technologies," in Proceedings of SPIE, 22nd Annual BACUS Symposium on Photomask Technology, vol. 4889 (Bellingham, WA: SPIE, 2002), in press.

19. AJ Merriam and JJ Jacob, "High-Resolution Photomask Phase Measurement Tool," in Proceedings of SPIE, 22nd Annual BACUS Symposium on Photomask Technology, vol. 4889 (Bellingham, WA: SPIE, 2002), in press.

20. R Jonckheere, "2002 Update on SEMI Standards Task Force on Photomask Qualification Terminology," in Proceedings of SPIE, 22nd Annual BACUS Symposium on Photomask Technology, vol. 4889 (Bellingham, WA: SPIE, 2002), in press.


Yasutaka Morikawa is assistant manager of the semiconductor components laboratory, semiconductor components operations of Dainippon Printing (Saitama, Japan), where he is responsible for phase-shifting mask development of altPSM, EAPSM, and other types of leading-edge photomasks. He joined the company in 1986, working on inspection and repair systems applications for high-end reticles and photomask blanks. He received a BS in chemical engineering from Tokushima University, Japan, in 1986. (Morikawa can be reached at +81 49 2781687 or morikawa_y@cc.micro.dnp.co.jp.)

Naoya Hayashi is general manager of the semiconductor components laboratory, semiconductor components operations at Dainippon Printing. Over the past 23 years, he has been responsible for the development of electron-beam exposure systems, resist materials and processes, phase-shifting materials, and etching technologies. He has been steering committee chair of Photomask Japan 2001/2002, BACUS session cochair for several years, and a member of Working Group 5 (Lithography) of the Semiconductor Technology Roadmap Committee of Japan. He received a BS in applied chemistry and an MS in electric chemistry from Tokyo Institute of Technology, Japan. (Hayashi can be reached at +81 49 278 1680 or hayashi_n@mail.micro.dnp.co.jp.)

Linyong Pang, PhD, is the product manager for the Virtual Stepper system at Numerical Technologies (San Jose), where he is responsible for product enhancement and advanced mask-defect printability analysis software. Before joining the company, he held engineering and management positions at Acuson's R&D lab, where he invented and developed FreeStyle, an extended-field-of-view imaging product. Pang holds nine patents and has eight others pending. He received a BS and MS in mechanical engineering from the University of Science and Technology of China in Hefei, Anhui, People's Republic of China, and a PhD in mechanical engineering and an MS in computer science from Stanford University in Palo Alto, CA. (Pang can be reached at 408/273-4330 or lpang@numeritech.com.)

Gerard T. Luk-Pat, PhD, is responsible for algorithm and software development at Numerical Technologies, which he joined in 2002 as a staff engineer in the Virtual Stepper group. Previously, he worked on digital subscriber line modems for Globespan Virata and magnetic resonance imaging research at the Mount Sinai School of Medicine in New York City. Luk-Pat holds one patent and has one pending. He received a BS in physics from the Massachusetts Institute of Technology in Cambridge, MA, and an MS and PhD in electrical engineering from Stanford University in Palo Alto, CA. (Luk-Pat can be reached at 408/273-4425 or gerard@numeritech.com.)


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