With the dawn of the new millennium, paradigms have been shifting in the semiconductor industry, particularly in Japan. At one time, the driving force in the semiconductor market was mainframes; then came a shift toward personal computers. Subsequently, digital consumer electronic products have come to dominate the industry, which will be replaced by broadband-networked products in the near future. Combining consumer, networking, and PC applications, digital convergence will create new broadband-networked markets based on a platform of audiovisual and information technologies.¹ The main points of the paradigm shifts in the industry are summarized in Table I.

DRAM Era System-on-a-Chip Era Personal computer Networked digital consumer electronics DRAM System LSI (or SOC) Capital spending Knowledge creation on silicon Commodity sales Solution offering Long cycle times (longer than 3 years) Short cycle times (typically a few months Table I: Paradigm business shifts in the semiconductor industry.

In accordance with this trend, the driving force of the semiconductor industry has been shifting from the fabrication of dynamic random-access memory (DRAM) chips for computer applications to system large-scale integration (LSI) and system-on-a-chip (SOC) applications, mainly for the consumer electronics industry. Under pressure from larger commodity DRAM suppliers overseas as well as from the economic situation known as the "DRAM recession," most Japanese device manufacturers have retreated from the DRAM market and begun to concentrate on high-end SOC manufacturing.

Technology Area DRAM Era System-on-a-Chip Era Product mix Low High Product volume High Low or variable Fab size Megafab Minifab (or multiple miniline fabs1) Market driver High throughput Short cycle times Process model Batch processing Single-wafer processing Inspection model Long-loop feedback Short-loop feedforward Yield management Steady enhancement Prompt, accurate estimation

Table II: Paradigm technology shifts in the semiconductor industry.

DRAM and SOC manufacturing have completely different business models, as shown in Table II. The DRAM business model involves the fabrication of high-volume, low-mix products, where the key to success is the highest throughput backed up by huge capital expenditures. In contrast, the SOC business model involves the fabrication of low or variable volumes of many types of consumer electronics devices, where short cycle times are demanded by SOC customers or end-product suppliers seeking to maximize timely sales of fashionable consumer products. In the rapidly changing era of the broadband Internet, consumers' interests have become more diversified and whimsical. The life cycles of consumer products can be as short as a few months. Consequently, total production volumes of digital consumer electronics products typically range from several thousand to perhaps 30,000. Production methods have shifted accordingly, from the traditional conveyor-belt system to the "cell" system, in which a device can be completely fabricated by a single worker. In the SOC business, knowledge creation or sophisticated value addition on silicon substrates is another key to success.

Growing Trend toward Single-Wafer Processing

In general, semiconductor device manufacturing and its supporting equipment toolsets have traditionally been designed for high-volume production of such products as DRAM devices. The large investments associated with megafabs sometimes cause overcapacity in the market and result in so-called silicon cycles, making semiconductor manufacturing a risky business.

The minifab concept, on the other hand, appears to minimize the gap between supply and demand by relying on small production lines that can be added step by step, require comparatively low levels of capital investment, and can adjust flexibly and quickly to changing consumer tastes, as illustrated in Figure 1. In addition to its high-mix, low-volume nature and its investment advantages, minifab manufacturing enables faster ramp-up times, shorter cycle times, and lower energy consumption and emissions levels than megafab manufacturing.

Figure 1: Production volume over time at a megafab (a) and a minifab (b). New lines can be constructed promptly at minifabs to meet demand.

Figure 2 shows the wafer processing capacity of each tool per process per month in one of Sony's 200-mm CMOS volume-production lines in Japan. The figure demonstrates that production capacity varies significantly from tool to tool. Even in this megafab, with its large production volume of 10,000 or 20,000 wafers per month, batch-process tools—such as oxidation, diffusion, low-pressure CVD, and wet-cleaning equipment—have excess capacity. In order to achieve a high tool-utilization ratio with current toolsets, an economically proper–sized fab will naturally be large.

Figure 2: Wafer-processing capacity of each tool per process per month on a 200-mm CMOS volume production line. Excess capacity leads to wasted investment and energy resources.

If the minifab concept were to be implemented with current toolsets, it would not be cost-effective because most tools have excess production capacity, which translates into both excess investment and wasted energy. Therefore, tools suitable for minifabs will not be the same as those found in current megafabs. Large-capacity equipment is wasteful in the mini-fab setting, where equipment must be downsized and redesigned to be able to perform multiple processes without causing cross-contamination. Minifab tools will have much lower throughputs than their megafab counterparts, and they will also have to be less expensive. Single-wafer processing equipment, including wet cleaning tools, must be installed in the minifab instead of the batch-processing tools preferable in the megafab.

An example of a minifab is illustrated schematically in Figure 3. Employing a minienvironment system, localized clean environments that isolate wafers from the ballroom air and personnel, the minifab cleanroom will drastically reduce the amount of space occupied by ultraclean areas and minimize electricity consumption. To avoid the adsorption of airborne chemical contaminants such as organic volatiles on silicon surfaces, wafers will be stored in closed pods.^2–4 Clean air free of chemical contaminants will be supplied to very limited enclosed areas for specific wafer processes, including postcleaning steps. During such steps, chemical contaminants have a detrimental impact on the performance of semiconductor devices, causing the degradation of gate oxide integrity, the incubation of CVD film, and the formation of haze on the wafer surface.^5,6

Figure 3: Schematic diagram of a minifab.

The Importance of Wet Cleaning Processes

As semiconductor device geometries continue to shrink and die sizes grow, microcontaminants such as particles, metallic impurities, and trace organic contaminants will have an ever-increasing detrimental impact on device yield and reliability.² Every wafer process step in ULSI manufacturing is a potential source of such contaminants, which may lead to defect formation and device failure. Scrupulous maintenance of clean wafer surfaces throughout the wafer-processing cycle is essential to obtain high yields. Rigorous wet cleaning is known to be effective in reducing the presence of these contaminants on the wafer surface, making it the most frequently repeated step in any LSI manufacturing sequence.⁷

Wafer-cleaning chemistry has remained essentially unchanged over the past 30 years. Hydrogen peroxide–based chemistry is the most prevalent cleaner in the semiconductor industry worldwide. Most notably, it is used to perform RCA standard cleans, in which wafers are sequentially immersed for several minutes in an NH^₄OH-H^₂O^₂-H^₂O mixture (SC-1) and an HCl-H^₂O^₂-H^₂O mixture (SC-2) at elevated temperatures, and then in dilute HF at room temperature. In immersion-type wet chemical cleans, even if ultrapure chemicals are introduced and then disposed of after each wafer-cleaning treatment, contaminant-removal efficiency is compromised by impurities brought into the fresh solution by incoming wafers.⁸

To meet increasingly stringent wafer-cleanliness requirements, new cleaning methods, including single-wafer spin cleaning in which fresh chemicals are continuously supplied to the wafer, must be implemented.⁸ If single-wafer spin cleaning is used in the wet etching of films on silicon substrates, better etch uniformity is expected from wafer to wafer and lot to lot. Single-wafer cleaning equipment has a much smaller footprint than a conventional wet bench and is the most suitable tool for short-cycle-time minifab operations for system LSI production. The tool's throughput, however, must be increased and its chemical consumption reduced. To solve these problems, the best approach is to develop ways to use alternative cost-effective chemicals that react more rapidly and use fewer chemicals than those used in conventional RCA cleans. The implementation of new chemistries will also reduce the volume of effluents generated during the cleaning process.

Additionally, the trend toward LSI device shrinkage will change gate-insulator materials and their formation methodologies from silicon dioxides thermally grown in a batch to silicon nitride/oxide gate stacks formed in a batch or on a single-wafer. Finally, high-k dielectrics will be deposited by means of single-wafer atomic-layer deposition. In accordance with these trends, pregate cleaning will naturally shift from batch processing to single-wafer processing.

All of these motivations and challenges are behind the development of a new single-wafer spin cleaning process at a Sony facility in Japan.

Implementing a New Single-Wafer Spin Cleaning Technology

The new, environmentally friendly system—single-wafer spin cleaning with repetitive use of ozonated water and dilute hydrogen fluoride (SCROD)—uses ozonated water and dilute HF without any additives or megasonic aids. As shown in Figure 4, the system functions by alternately applying ozonated water and dilute HF onto a wafer surface for a few seconds, a cycle that can be repeated as many times as necessary until the surface attains the required level of cleanliness. Following the last dilute-HF treatment, either DI water is applied to the wafer to obtain a hydrophobic silicon surface or ozonated water is applied to obtain a hydrophilic silicon surface. Then spin drying takes place in a nitrogen atmosphere to prevent spot formation on the patterned wafers.

Figure 4: Schematic diagram showing the repetitive use of ozonated water and dilute HF in the SCROD process.

The system's short-time- cycle cleaning can efficiently remove particulate and metallic contaminants, as well as trace organic contaminants, without increasing the microroughness of the silicon surface.²

Particle Removal. Figure 5 compares the particle-removal efficiency of a single-wafer spin-cleaning SC-1 procedure and SCROD cleaning. While 1 minute or 3 minutes of SC-1 spin cleaning cannot remove surface particles effectively, a 1-minute, 3-cycle SCROD cleaning can remove 87% of Al^₂O^₃ particles, 97% of SiN particles, and 99.5% of polystyrene latex (PSL) particles. Even a one-cycle clean can remove 79% of Al^₂O^₃ particles, 86% of SiN particles, and 98% of PSL particles. (Clearly, SiN and PSL particles are more easily removed from the wafer surface than Al^₂O^₃ particles.) Removal efficiency does not depend on particle size down to 0.8 µm, the smallest size detected during this study.

Figure 5: Comparison between the particle-removal efficiencies of single-wafer SC-1 versus SCROD cleaning.

The system removes particles as follows. During ozonated-water treatment, a chemical oxide film grows very rapidly on the wafer surface, becoming almost saturated and very thin after a few seconds. This chemical oxide can be completely etched from the wafer surface in a few seconds by the subsequent application of dilute HF. After the chemical oxide has been completely removed from the wafer surface during the dilute-HF treatment, particle-removal efficiency has almost reached its peak. If some particles remain on the wafer surface, they are removed during the next cycle.

While SCROD cleaning can remove particles from silicon substrates, it also can be successfully used to remove thin films that form on the silicon surface, including silicon dioxide, silicon nitride, tungsten silicide, and polycrystalline silicon. Thin-film removal is achieved by controlling the cleaning conditions, such as the number of cleaning cycles and dilute-HF pouring times. Furthermore, by increasing the concentration of ozonated water, a typical 10-second cleaning cycle can be shortened to only a few seconds to save time and decrease chemical and water consumption.

Metal Removal. Iron contaminants on the wafer surface as high as 10¹² to 10¹³ atoms/cm² are reduced to ≤10⁹ atoms/cm² with only one repetition of a 20-second ozonated water and dilute-HF treatment. Likewise, with just one repetition of a 20-second treatment, aluminum contamination is reduced to the detection limit of 4 X 10⁸ atoms/cm². While most of the iron and aluminum atoms on the wafer surface are ionized and dissolved into the ozonated water, some iron and aluminum atoms remain in the chemical oxide grown during the ozonated-water treatment because these atoms have a higher oxide generation enthalpy than silicon. However, the oxide-trapped atoms are dissolved when the chemical oxide on the wafer surface is removed with dilute HF. The iron and aluminum ions dissolved in the dilute HF are not redeposited on the wafer because they have a lower electronegativity than silicon. That accounts for their very high removal efficiencies.

Figure 6a illustrates the efficiency over time of using an initial ozonated-water treatment to remove copper contaminants from the wafer surface. While copper contamination decreases rapidly during the first 10 seconds of treatment, it becomes almost saturated after 30 seconds. Since ozone has a higher oxidation-reduction potential than copper, it first dissolves the copper oxidatively. However, the copper contaminants are covered with a chemical oxide grown during the prolonged presence of ozonated water on the wafer surface, and that chemical oxide obstructs the dissolution of the copper atoms by the ozonated water. Consequently, the efficiency of the copper removal procedure gradually decreases and finally peaks.

The copper atoms remaining on the wafer surface after the ozonated-water treatment are uncovered by etching the chemical oxide during a subsequent dilute-HF treatment. This treatment also removes copper atoms incorporated into the chemical oxide by lifting off the chemical oxide. The uncovered copper atoms are then easily dissolved by the next ozonated-water treatment. Repeated ozonated-water and dilute-HF cleaning cycles are more effective at removing copper than longer chemical application times.^9,10 Copper ions dissolved in solution do not redeposit onto the wafer surface because they are immediately washed away through the spin cleaning process. As the number of cleaning cycles increases, surface contamination gradually decreases, as shown in Figure 6b. Copper contamination is finally reduced to the level of 1 X 10⁹ atoms/cm² or lower using this cleaning method. The chemical process involved in copper removal is illustrated in Figure 6c.

Figure 6: (a) copper contamination on the wafer surface before and during the application of ozonated water; (b) copper contamination on the wafer surface before SCROD cleaning and after one, three, six, and nine SCROD cycles; and (c) the chemical process involved in removing copper from the silicon substrate.

Organic Removal. Ozonated water has a sufficiently high oxidation potential to degrade organic contaminants oxidatively. Dilute HF can remove the contaminants by lifting them off the native oxide film on which they are adsorbed.

Surface Roughness. Unlike technologies that involve the simultaneous application of HF and ozonated water (e.g., SC-1 cleans), repetitive SCROD spin cleaning does not produce surface roughness.

Figure 7: Time-zero dielectric breakdown and time-dependent dielectric breakdown data comparing the effects of an immersion-type RCA clean and SCROD on gate-oxide integrity.

Gate-Oxide Integrity. The use of the SCROD technique, in which fresh chemicals and water are continuously supplied to the wafer surface, provides better gate-oxide integrity in MOS transistors than conventional immersion-type RCA cleaning, in which metallic contaminants accumulate in the solution. Figure 7 shows the time-zero dielectric breakdown (TZDB) and time-dependent dielectric breakdown (TDDB) of gate oxides cleaned using a conventional RCA versus a SCROD process. For both TZDB and TDDB, the SCROD clean offered better results than the immersion-type RCA clean, indicating that fresh chemicals and water are key factors in achieving high gate-oxide integrity.⁸

Figure 8: Chemical and DI-water consumption comparisons among different cleaning methods.

Chemical and Water Consumption. SCROD cleaning consumes far smaller quantities of chemicals and DI water than a traditional immersion-type RCA cleaning, as shown in Figure 8. In the SCROD process, effluents can be easily controlled, and the disposed ozonated water spontaneously decomposes into oxygen and water. The disposed HF can be used to produce pure HF and other fluoride chemicals in the form of fluorite for the use of the chemical industry.

Conclusion

A growing trend in broadband-networked digital consumer electronics has led to paradigm shifts in semiconductor manufacturing toward shorter cycle-time minifab operations, where single-wafer cleaning is desired. Other industry forces driving toward single-wafer cleaning include increasingly stringent surface contamination control requirements, the need for environmentally friendly technologies, and the drastic changes required of gate-insulator materials and forming methods.

An example of the trend toward single-wafer processing in minifab operations is the SCROD technology, which alternately uses ozonated water and dilute HF at room temperature. This low-cost, high-performance cleaning method, in which fresh liquids are continuously supplied to the wafer surface, has already been implemented on Sony's 200-mm PlayStation2 chip-manufacturing lines in Nagasaki, Japan, and on the 300-mm CCD imager/LCD microdisplay device-manufacturing lines in Kumamoto, Japan.

Semiconductor process engineers, cleanroom designers, equipment suppliers, and researchers in academia should work more closely to perfect ultraclean single-wafer transport and process environments as part of a well-balanced, total approach to developing future minifabs.

References

1. "IBM, Sony, Toshiba to Develop Chip Technologies Jointly," (Armonk, NY: IBM, 2002); available from Internet: http://www.ibm.com/news/us/2002/04/02.html.

2. T Hattori, "Chemical Contamination Control in ULSI Wafer Processing," in Proceedings of the Characterization and Metrology for ULSI Technology 2000 Conference (New York: American Institute of Physics, 2001), 275–284.

3. K Saga and T Hattori, "Identification and Removal of Trace Organic Contamination on Silicon Wafers Stored in Plastic Boxes," Journal of the Electrochemical Society 143, no. 10 (1996): 3279–3284.

4. K Saga, H Kuniyasu, and T Hattori, "Prevention of Increased CoSi^₂ Sheet Resistance by Storage of Silicon Wafers in a Closed Pod," Electrochemical and Solid-State Letters 2, no. 6 (1999): 300–302.

5. K Saga and T Hattori, "Influence of Silicon Wafer Loading Ambients in an Oxidation Furnace on the Gate Oxide Degradation Due to Organic Contamination," Applied Physics Letters 71, no. 25 (1997): 3670–3672.

6. K Saga and T Hattori, "Influence of Surface Organic Contamination on the Incubation Time in Low-Pressure Chemical Vapor Deposition," Journal of the Electrochemical Society 144, no. 9 (1997): L253–L255.

7. T Hattori (ed.), Ultra Clean Surface Processing of Silicon Wafers—Secrets of VLSI Manufacturing (Heidelberg, Germany: Springer-Verlag, 1998).

8. T Osaka and T Hattori, "Influence of Initial Wafer Cleanliness on Metal Removal Efficiency in Immersion SC-1 Cleaning: Limitation of Immersion-Type Wet Cleaning," IEEE Transactions on Semiconductor Manufacturing 11, no. 1 (1998): 20–24.

9. T Hattori et al., "Contamination Removal by Single-Wafer Cleaning with Repetitive Use of Ozonated Water and Dilute HF," Journal of the Electrochemical Society 145, no.9 (1998): 3278–3284.

10. T Osaka et al., "Single-Wafer Spin Cleaning with Repetitive Use of Ozonated Water and Dilute HF ("SCROD")," in Proceedings of the Seventh International Symposium on Cleaning Technology in Semiconductor Device Manufacturing (Pennington, NJ: The Electrochemical Society, 2002), 3–14.

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Takeshi Hattori, PhD, is the chief research officer and general manager of UCT Laboratories, Sony Semiconductor Network in Atsugi, Japan. He has worked for Sony for more than 30 years, except during a leave of absence when he worked on MOS process R&D at Stanford University (Palo Alto, CA). Hattori is a member of the editorial advisory board of MICRO, a member of the organizing committee of the International Symposium on Solid State Devices and Materials (sponsored by the Japan Society of Applied Physics [JSAP]), and an executive committee member of the International Symposium on Semiconductor Manufacturing sponsored by IEEE, SEMI, and JSAP. He also belongs to the executive committee of the Electrochemical Society's electronics division and is a member of SEMI's regional standard committee in Japan. He received BS, MS, and PhD degrees in electrical and electronic engineering from Sophia University in Tokyo and a DEng from Stanford University. (Hattori can be reached at +81 46 2305461 or takeshi.hattori@jp.sony.com.)