GOT INGOTS: After a steep drop in 2001, total silicon area shipments will grow slowly through 2005. SOURCE: SEMI/SMG CONSENSUS FORECAST

Wafer prices are poised for an increase over the next two to five years, predicts a specialist with a leading chipmaker. Semiconductor manufacturers can expect shortages of both 200- and 300-mm substrates shortly after semiconductor consumption returns to the levels that existed at the end of 2000. Looking further into the future, the industry faces additional obstacles in the transition to 450-mm wafers as well. The semiconductor industry was on the cusp of a shortage as 2001 approached, David Myers noted in his presentation at SEMI's recent Microelectronics Materials Strategy Symposium in San Jose. Since then, silicon suppliers have not expanded capacity. Hence, any return to a semblance of profitability for the industry will trigger an increase in wafer prices.

"Nobody's been making any money in silicon for the past several years," says Myers, a senior member of Texas Instruments' technical staff in worldwide procurement and logistics. When the market gets healthier, suppliers will invest in 200-mm, not 300-mm, capacity, and the potential exists for additional problems. Chipmakers may tighten specifications in order to maintain yields during device shrinks, and capital investment will be needed in order to upgrade wafer-manufacturing tools and processes. Further capacity constraints will result, Myers says.

As a result, the silicon wafer specialist foresees two scenarios. Either wafer prices will rise an unspecified amount, or the industry will take desperate cost-reduction measures that will force it to forgo "strategic actions" such as the development of 450-mm wafers. An eventual transition to 450-mm substrates "has to happen to prevent factory obsolescence on the part of device houses," Myers insists.

Staying on course with Moore's law requires periodic increases in wafer diameter, he says. That magnifies the importance of a 450-mm transition. The dictum by Intel's cofounder demands an annual improvement of 25–30% in cost per function. This improvement has four elements, according to Myers, citing a recent paper in Semiconductor Silicon/2002 by Goodall, Fandel, Allan, Landler, and Huff. These elements are reductions in feature sizes of 12 to 14%; a 4% upgrade in wafer size; a yield improvement of 2%; and productivity gains of 7 to 10%. Yield improvements are no longer available. Productivity gains involve increased factory efficiency and related improvements.

The above calculations mean that shrinks account for approximately 50% of the requirements for staying on Moore's law, other elements 35% or so, and an increase in wafer size the remaining 15%. Myers emphasizes, however, that as beneficial as that 15% more silicon real estate is, periodic increases in wafer diameter are even more significant because of their timing. Chipmakers need the 30 to 50% productivity boost so that they can "fund the factory upgrades required by device shrinks."

If the transition to 450-mm substrates is not technically feasible by 2012 then the industry will need to find alternatives to round silicon wafers, according to Myers. And if the wafer producers have the technical chops but lack the funds, silicon purveyors will have to consolidate.

"By 2011 there will be only one silicon company left," the TI specialist predicts. "Where do wafer companies get their productivity boosts from? They don't, and that puts a world of hurt on them." Nevertheless, he admits he could be wrong, noting that "12-in. wafers were about as plausible as antigravity."

Myers suggests a range of options if a 450-mm transition is neither technically nor commercially viable. The options are continuous-flow processing using ribbons or fluids; high-speed single-chip processing; and two-sided processing on 300- and 400-mm wafers only. Further possibilities are three-dimensional scaling; noncrystalline substrates; reusable substrates; and nanotechnology, or making devices atom by atom.

Myers's September presentation on the future of silicon wafers ranged over a variety of issues. He notes a "continued and relentless pressure" to reduce the size specification for killer particles. Why? "Wafer fab engineers believe in their heart of hearts" that particles limit yield, and that these losses are tied to particle size as it relates to node dimension. Metrology problems in this regard will be resolved, and fabs will clamor for high-resolution systems for characterizing equipment and for process control. Myers asserts that process capability below 90 nm will be a difficult and expensive proposition involving cleanrooms, chemicals, and equipment.

Regarding edge exclusion through 2007, the TI specialist foresees edge exclusion moving from 3 mm to 2 mm around 2004, give or take one year. Because the metrology and fab equipment won't be available, chipmakers can forget moving from 2-mm to 1-mm edge exclusion for the foreseeable future.

As for all-important flatness, Myers points out that the current metrics involving SFQR and the like will be replaced with "more-demanding" specifications by 2004. There are two reasons for the change. One is that the current metrics do not adequately reflect stepper performance in relation to wafer topography in areas such as the interaction between the wafer and the chuck, for example. The second reason is that the amount of information available from an SFQR measurement is too low at approximately 36 points for 200-mm wafers, and 88 points for 300-mm wafers.

The proposed new metric for flatness is "flying-site SFQR," Myers says. This metric technology maps an area measuring 25 X 8 mm on all possible wafer locations to a resolution of 1 mm. As a result, the map's information density is 100 points per square centimeter in relation to stepper performance, regardless of the die layout. In addition, the industry will adopt nanotopography specifications and create a new metric for edge rolloff.

The new flatness metric should not require major capital investment for 300-mm wafers until chipmakers exhaust productivity gains from double-sided polish around 2005, Myers says. However, the pressure for improvements in this area "will be as relentless" as they are for particle reduction.

The TI specialist does not hold out much hope for the future of silicon-on-insulator (SOI) wafers primarily because of cost considerations. Work on SOI is "dominated primarily by technologists. These guys are completely divorced from reality, in my opinion." Although he says wafer cost dominates the discussion of SOI, other issues come into play. These include an edge-exclusion factor of 5 mm, metrology concerns, nonuniformity, and particle/defect specifications.

On the materials front, Myers cites several silicon modifications now under consideration. Strained silicon, high-resistivity substrates for RF use, and heterojunctions are a few of the developments. Because it is inherently limited, silicon requires modification. Myers says epitaxy is the preferred method of modification, because it easily works with the silicon lattice structure. He notes that annealed wafers and crystal orginated particle-free p/w wafers may offer solutions for only a few nodes. He foresees an increase in the diversity of wafer products. A final prediction: bulk silicon will not survive past the 45-nm technology node.