This article describes how Infineon Technologies (Dresden, Germany), a memory manufacturer, used the real-time classification (RTC) feature on an AIT II high-throughput patterned-wafer inspection tool from KLA-Tencor (San Jose) to systematically investigate post-oxide-CMP cleaning.^3,4 The binning capability of RTC allowed the facility to focus on defects of interest while filtering out nuisance defects and, at the same time, achieve real-time visibility into the effectiveness of various cleaning-process parameters and their potential impact on final device yield. Other features of the inspection tool include high sensitivity, low-angle laser illumination, and an integrated optical review microscope. The oblique laser incidence provides for robust measurements of the thickness variations and roughness of CMP layers.

Experimental Procedures

Unpatterned TEOS test wafers with an initial oxide thickness of 750 nm were used in the experiment. Test wafers, rather than production wafers, were utilized both to minimize study costs and to allow the researchers to disregard process variations and excursions while using highly sensitive inspection recipes. For valid results, however, conditions for the test wafers at the interlayer dielectric process step must be the same as those for production wafers.

The CMP process was performed on polishers from Speedfam-IPEC (Chandler, AZ) using a silica-based slurry. Polishing was followed immediately by a rinse procedure to achieve some initial reduction in the level of chemically and physically bonded slurry residuals on the wafer surface. Mechanical brush scrubbing was then performed using double-sided scrubbers in an aqueous environment. The cleaning efficiency of the rinse depends on process time and rinse media. This experiment compared a standard rinse (recipe A) that uses only DI water with a modified rinse (recipe B) containing diluted ammonia.⁵

For the defect density measurements, inspection parameters of the AIT II were as follows: unpatterned wafer, 10-µm laser spot, circular incident polarization without a polarization filter in the detection unit, and 0.3-µm sensitivity on each of the two channels. This sensitivity level was chosen because at about 0.18 µm the number of false alarms exceeds 10%. The tool's integrated optical microscope and a scanning electron microscope (SEM) were used for defect review. Two RTC features—"size" (anomalous pixel area) and "single-/multichannel detection" (i.e., whether a defect type is detected in one or both channels)—were used for defect classification. The RTC tool's bins 7, 8, and 9 were not occupied in the fab's defect list, so those bins were used to represent size, with a second digit added to represent single- or multichannel detection (see Figure 1). For example, defects in classes 71 and 72 were detected on a smaller pixel area than defects in the other classes. Those in class 71 registered only in one channel, while those in class 72 were measured in both channels.

Figure 1: Defect binning scheme set up by the RTC tool. The numbers 7, 8, and 9 represent size characterization; the second digits, 1 and 2, represent single- and multichannel detection, respectively.

Results and Discussion

Test runs in which the post-CMP rinse procedure parameters were varied systematically made it possible to classify defect types with differing shapes, sources, and kill rates down to 200 nm. Figure 2 shows optical microscope and SEM images of the two major types:
flat, chopstick-shaped particles consisting of silicon oxide and slurry agglomerations. In general, there were also an average of three or four macroscratches per wafer. The chopstick-shaped particle defects tended to be captured by only one channel, while the slurry agglomerations, which resemble polystyrene latex spheres, tended to be captured by both channels. For the multichannel bins 72, 82, and 92, the SEM review results demonstrated a correlation between the different anomalous pixel areas and the defects' physical size, which are presented in Table I. Electrical characterization results showed that the post-CMP defects primarily affected the wafer's subsequent metallization layer. The slurry agglomeration defects had the greatest impact on device yield, causing shorts between metal lines.

Figure 2: Optical microscope and SEM images of major defect types: Flat, chopstick-shaped particles (top), which are regarded as nuisance defects, and spherelike slurry agglomerations (bottom), which affect device yield.

Bin No. Anomalous Pixel Area Size Range (µm) 72 <100 <0.5 82 100–800 0.5–1 92 >800 >1

Table I: SEM review determined that the multichannel bins' anomalous pixel areas could be correlated with metric measurements of defect diameter.

In contrast, the flat, chopstick-shaped particles had no discernible impact on yield. Those captured were all comparable in size, with the majority found in bins 71 and 81. The scattering characteristic of these particles is strongly influenced by orientation, however, so that size information about specific defects is not very accurate. As a result, bins 71, 81, and 91 can be regarded as one class for practical reasons. In this study, when size information was disregarded, classification results for these bins exhibited a very high purity, and a manual review demonstrated that all defects from these bins were, in fact, flat, chopstick-shaped particles, which can be considered nuisance defects.

This finding dramatically reduced the number of defects of interest to about one-tenth of the defects identified, i.e., the agglomerations of slurry particles found only in bins 72, 82, and 92. Table II shows the accuracy and purity percentages for representative bins. Bin 81, which had a population of 50 chopstick-shaped defects, exhibited a purity of nearly 100%, whereas its accuracy wasn't determined explicitly. Bin 82 exhibited 89% accuracy and 58% purity, while for bin 92, the figures were nearly 100% accuracy and 85% purity. The variation in bin accuracy is primarily attributable to interchanges of slurry agglomerations between the bins resulting from laser focusing problems; because the large particles are of differing heights, they may exhibit different scattering behaviors.

Defect Classification Bin 92 Control Sample Bin 82 Control Sample Bin 81 No. of defects reviewed 59 61 101 57 50 No. of defects binned correctly 50 61 59 50 50 No. of defects not binned correctly 9 0 41 7 0 Purity 85% — 58% — 100% Accuracy 100% — 89% — —

Table II: SEM review of a subsample of bin populations determined the inspection tool's accuracy and purity performance for defects of interest (bins 92 and 82) and purity for nuisance defects (bins 81). The review strategy prevented researchers from checking the accuracy of bin 81.

The variation in purity in the multichannel bins is caused mainly by interference from flat, chopstick-shaped particles that are oriented in parallel to the laser beam and thus scatter in both channels. This effect can be roughly estimated based on the assumption that there is an equal distribution of the chopstick-shaped particles—that is, there is no preferred orientation of these defects owing to asymmetric hardware constellations. The estimation further assumes that both channels should detect these particles if their long axes deviate no more than ±10° from the direction of the laser beam. This would mean that approximately 11% (20°/180°) of the chopstick-shaped particles would fall into the
multichannel bins, and, as a result, the accuracy of bins 71, 81, and 91 can't exceed 90%. In any case, the accuracy of the single-channel bins is of limited usefulness since these bins do not contain defects of interest.

The classification of microscratches is strongly dependent on the shape of the defect. While continuing scratches that are not perpendicularly oriented to the laser beam will scatter light into only one channel, scratch marks in general will be detected in two channels. Because of the low defect counts that typically are found for bin 92, it is important to take into account the macroscratches and other prelayer defects within this class to ensure that cleaning-process optimization efforts focus on those defects caused by the CMP process.

In addition to investigating defect types, the experiment also compared total and killer defect densities for wafers treated with a standard rinse with those of wafers treated with a modified rinse. Defect density was then correlated with rinse time. Figure 3 presents the relationship between the numbers of defects detected per wafer and both rinse time and recipe for bin 92. The polishing tool has five carriers, leading to the possibility of systematic deviations attributable to the influence of the different carriers. To compensate for this, only mean values of defect counts are presented in the figure. In addition, the defects associated with preprocessing and macroscratches were subtracted from the measured defect counts. As the figure indicates, increasing rinse time from 5 to 50 seconds with the modified rinse recipe B decreased the number of flat, chopstick-shaped particles in bin 92 by 15%, but the number of slurry agglomerations remained fairly constant. This finding ruled out total defect count as a means of tracking the number of killer defects.

Figure 3: The relationship between total and killer defect counts and rinse conditions for bin 92.

The figure also shows that when results with the standard rinse are compared with those for the modified rinse, the total number of defects is approximately the same when the rinse time is equivalent. When the modified recipe B is used, however, the number of defects in bin 92 (the killer defect category) is one-tenth that found when using recipe A with the same rinse time. Based on these results, the modified rinse recipe B is clearly superior to the standard rinse recipe A because it not only can reduce overall defect counts, it is more effective at removing the killer defects caused by slurry particles. On the other hand, the yield benefits of increasing the rinse time with recipe B appear to be minimal because the average number of slurry agglomerations remains fairly constant. As a result, the researchers concluded that the optimal cleaning procedure is to use the modified, diluted-ammonia recipe with a process time of 5 seconds. This conclusion is viewed as a compromise between maximizing device yield on the one hand, and minimizing both the process time and cost of consumables on the other.

Conclusion

An investigation of post-oxide-CMP cleaning revealed that there are two major defect types on the processed wafers: flat, chopstick-shaped particles, which were found to have minimal effect on yield, and slurry agglomerations, which lead to killer defects. Using the RTC option on an in-line inspection tool, it is possible to bin these yield-impacting slurry agglomerations separately, thereby reducing the number of defects of interest for cleaning-process optimization by 90%. Because the large slurry agglomerations are not represented linearly to the total defect counts, the binning of these killer defects can be used to track variations in the rinse procedure. The researchers also found that a modified rinse procedure using ammonia is approximately 10 times more effective than the standard DI-water rinse recipe in reducing the killer defects. The actual rinse time, however, is of minor importance, because it only influences the number of nuisance defects.

Acknowledgments

The work described in this article was supported by the EFRE fund of the European Community and by funding from the State of Saxony of the Federal Republic of Germany (project number 6327).

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References

1. J Curry, "Integrated Solutions for the Challenges of CMP," Semiconductor Fabtech, no. 1 (1996).

2. JM de Larios et al., "Evaluating Chemical Mechanical Cleaning Technology for post-CMP Applications," MICRO 15, no. 5 (1997): 61–67.

3. C Dennison, "Developing Effective Inspection Systems and Strategies for Monitoring CMP Processes," MICRO 16, no. 2 (1998): 31–41.

4. T Reuter et al., "Using Laser-Based Patterned-Wafer Inspection for Memory and Logic Applications," MICRO 17, no. 9 (1999): 89–95.

5. K Mikhaylichenko et al., "Comparing Contact and Non-Contact Technology for Post-CMP Cleaning," Semiconductor Fabtech, 11th ed., 2000.

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Kerstin Kaemmer, PhD, is a senior engineer for electrical failure analysis at Infineon Technologies (Dresden, Germany). Before joining Infineon in 1998, she received a degree in the field of superconductor physics and a PhD in materials science from the Technical University of Dresden. (Kaemmer can be reached at +49 351 8867055 or kerstin.kaemmer@infineon.com.)

Grit Bonsdorf, PhD, is a senior engineer for wet processes at the Infineon Technologies Memory Development Center in Dresden. Before joining Infineon in 1999, she was an engineer for wet process equipment at Steag Microtech in Pliezhausen, Germany. During those years she gathered experience in the field of wet cleaning and etching, post-CMP cleaning technologies, and copper electroplating. She received a PhD in chemistry from the Technical University of Dresden. (Bonsdorf can be reached at +49 351 8866776 or grit.bonsdorf@infineon.com.)

Martin Tuckermann, PhD, is a senior application engineer at KLA-Tencor (San Jose) for dark-field and bright-field patterned-wafer inspection systems. He is stationed at Infineon in Dresden. Before joining KLA-Tencor in 2000, he received a degree in the field of atmospheric physics from the University of Heidelberg, Germany, and a PhD in biophysics/materials science from the Technical University of Dresden. (Tuckermann can be reached at +49 351 8280223 or martin.tuckermann@kla-tencor.com.)

Jim Kavanagh is product manager for KLA-Tencor wafer inspection and Surfscan products in Central Europe. Before joining the company, he worked at Intel as a yield engineer and with the National Microelectronic Research Centre in Ireland as a research engineer of III-V semiconductor lasers. He received a BS in physics from the University of Essex in Colchester, UK. (Kavanagh can be reached at +44 777 6226624 or jim.kavanagh@kla-tencor.com.)