Figure 2: Number of deposited Ti atoms in an ALD TiN layer per unit area versus the number of cycles. Substrates shown are thermal oxide and PECVD oxide.

Two Important Parameters. Among other process parameters, two main factors affect the TiN film growth.^1,2 First, the initial growth of ALD TiN films is highly dependent on the surface properties. For instance, it is more difficult to achieve TiN surface closure on the thermal side than on the PECVD plasma (see Figure 3). Secondly, the NH₃ dose heavily affects TiN film growth and appreciably determines the growth rate. For very low ammonia dosing, the growth rate is significantly lower than that of the highest ammonia dosing settings. This behavior occurs because the reaction kinetics of the NH₃ with the TiCl bonds are quite slow at these low deposition temperatures.

Figure 3: The surface coverage of the substrate by ALD TiN versus the number of deposited Ti atoms in an ALD TiN layer per unit area. Substrates shown are thermal oxide and PECVD oxide.

ALD TiN and WCN Grown on Different Substrates: A Comparison

A diffusion barrier material must be compatible with different materials used in a dual-damascene structure, such as various low-k materials, etch stops, and copper. In this study, both TiN and WCN barrier films were deposited with ALD on wafers of copper, PECVD silicon dioxide, and silicon carbide hard masks, spin-on dielectrics like poly aryl ether and HSQ- and MSQ-based low-k materials, and CVD SiCO:H-type low-k materials. WF₆, NH₃, and triethylboron were used as tungsten-carbon-nitride precursors. Details of the processing and characterization have been reported elsewhere.³ The main results are summarized below: ALD WCN is seen to be preferable to ALD TiN as a diffusion barrier material for advanced metallization.

Deposition on Cu and Thermal Oxide. Severe contamination problems can occur during ALD TiN barrier deposition when the films are grown on copper wafers. The titanium nitride process can cause etching of the underlying copper lines because of the interaction of the TiCl₄ and NH₃ precursors with copper. By contrast, no volatile copper reaction products are generated when WCN is grown on a copper surface. Furthermore, the growth rates of WCN on a thermal oxide and on copper are considerably higher than in the case of titanium nitride, which from the perspective of throughput is a considerable improvement.

For a typical ALD process window, the WCN growth rate per cycle is 0.8–0.9 Å/cycle and 0.23 Å/cycle for TiN growth. The specific resistivity of WCN is 350–400 µΩcm. This is somewhat higher than in the case of TiN (which is 250–300 µΩcm), but still acceptable. When examining film composition, ALD WCN films can be seen to contain nanocrystallites, while TiN films are fully crystalline, with grain boundaries perpendicularly oriented to the substrate. So from the perspective of potential diffusion along the grain boundaries, WCN films also exhibit superior properties to their TiN counterparts.

Deposition on Porous Low-k Dielectrics. Atomic layer deposition of TiN and WCN on HSQ- and MSQ-type low-k materials with an interconnected pore structure faces some challenges. These materials have typical pore diameters of 4 nm. Experiments have shown that the TiN precursors diffuse throughout the whole dielectric stack, as demonstrated in Figure 4. Figure 4a is a TEM cross-section of an HSQ porous dielectric after deposition of ALD TiN, and Figure 4b details that the ALD precursors have penetrated the pore system, resulting in the deposition of TiN inside the film.

Figure 4: (a) TEM cross-section of a HSQ porous dielectric after the deposition of ALD TiN; (b) detail of the ALD precursors that have penetrated the pore system, resulting in the deposition of TiN inside the film.

During WCN growth on a porous MSQ material with a k value of 2.2, deposition also occurs throughout the film. The precursor gases do not seem to discriminate between the surface and the bulk material if there is a pathway available. As a result, a metallic barrier forms inside the dielectric, degrading the effective k value of the integrated low-k ALD stack. For these substrate materials, the atomic layer deposition method does not seem to offer a control mechanism that enables selective deposition on the surface but not in the pore structure.

CVD SiCO:H materials have an interconnected pore structure on a different level than the MSQ materials. An adequate sealing of the surface can prevent deposition inside the pores of these materials. Atomic layer deposition of WCN was done on a CVD SiCO:H film, which was fully sealed by a nitrogen plasma treatment. The film turned out to be continuous without major growth inhibition effects and without diffusing into the porous low-k dielectric.

In summary, the compatibility of WCN with the various low-k materials and copper indicates that ALD WCN is an attractive diffusion-barrier material for advanced metallization. Table I lists the sheet resistance and uniformity of WCN thin films grown on different substrates.

Substrate Thickness (nm) Rs (W/sq r) Standard deviation (%) Thermal SiO2 ~10 443 4.8 PECVD SiC ~10 425 3.8 Plasma-sealed porous CVD SiCO:H ~10 390 3.0 As-deposited. porous CVD SiCO:H ~10 130–425 31.1 Thermal SiO2 27 149 6.8 Plasma-treated aryl ether 26.5 141 3.1 As-deposited aryl ether 24 167 4.9

Table I: Summary of sheet resistance and uniformity of WCN thin films grown on different substrates.

The 65-nm Technology Node

The CMOS 65-nm technology node will likely be the insertion point for the use of ALD barriers, so it is important to investigate the barriers' compliance with the node's requirements, which are predicted by The International Technology Roadmap for Semiconductors (ITRS). There are three key requirements to examine for the metallic diffusion barrier: geometric, thickness, and low-k material compatibility.

Geometric Requirement. The geometric requirement refers to the capability to deposit barrier films in narrow dimensions. It is expressed as pitch (sum of the trench width and the spacing between two neighboring trenches) and aspect ratio (ratio of height over the width of the trench or the via). The ITRS lists the pitch and aspect ratio of the interconnect structure at the 65-nm node. For instance, at the intermediate wiring level, the width of the wire is about 100 nm, while the aspect ratio of both the wire and the via is about 3.4:1. Because of the high step coverage of the ALD technique, the geometric requirements will most likely be met.

The impressive step coverage achieved by the ALD technique is presented in Figure 5, which shows a cross-section of a via that has been covered with an ALD barrier. The depth of the structure is about 55 µm and the diameter is about 0.475 µm, resulting in an aspect ratio of more than 100:1, with a still-acceptable coverage of the via's sidewall. The dimension of the via differs considerably from that of the structures used in CMOS interconnects, but it still illustrates ALD's step coverage capabilities.

Figure 5: Cross-section of a via, covered by an ALD barrier (via depth: 55 µm, via diameter: 0.475 µm). (Courtesy of Philips Research Leuven).

Thickness Requirement. Thin barriers must optimize the wire resistance. The ITRS proposes that barrier thickness be scaled so that it does not consume more than 15% of the width of the wire. For the intermediate level of an 65-nm structure, this implies a barrier thickness of not more than 7–8 nm. It has been argued elsewhere that the minimum barrier thickness should be at least the thickness necessary to close the substrate surface.⁴ For example, when the ALD WCN process is performed on an as-grown thermal oxide substrate at 350°C, the surface closes at about 5 nm. Taking into account the within-wafer uniformity—that is, the minimum barrier thickness on the wafer should occur with a probability of at least 99.7% or 3σ—a minimum thickness of 5–6 nm is needed. A safety margin of a few extra nanometers should be added in order to protect the underlying oxide from hydrofluoric acid. This value does not exceed the ITRS recommendations for the 65-nm node, thus fulfilling the thickness requirement. These results depend on the process conditions as well as on the substrate on which the layers are grown.

Low-k Material Compatibility. In porous dielectric films, two bottlenecks must be addressed: first, the lack of suitable functional groups at the surface, and second, the penetration of the ALD precursors through the pore system. The latter has been discussed before; the substrate surface has to be adequately sealed. The availability of suitable functional groups relates to the substrate-dependent growth of the ALD films. It has been observed that TiN growth does not proceed well on as-deposited SiOC:H films.⁵ The SiOC:H surface was assumed to contain many fewer functional groups than an oxide substrate on which the ALD precursors can attach themselves. Therefore, a surface pretreatment, compatible with the low-k material, is necessary to enable the growth of the ALD films. For SiOC:H films, an appropriate oxygen plasma treatment, such as a reactive ion etch oxide plasma, can serve this purpose.

Conclusion

Atomic layer deposition shows great promise as a technique for the deposition of copper diffusion barriers. The ALD WCN layer demonstrates good barrier properties and is compatible with different substrate materials. Porous dielectric materials, however, require solutions such as pore sealing prior to ALD barrier deposition to prevent the diffusion of precursors into the porous material. Preliminary investigations indicate that the ITRS's 65-nm technology node requirements can be met, but only when preceding process steps are integrated in the process flow. These steps are necessary to seal the pores and prepare the surface of the dielectric stack for ALD.

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References

1. A Satta et al., "Nucleation and Growth of TiN Films Deposited by Atomic Layer Deposition," in Proceedings of the Third International Conference on Microelectronics and Interfaces (New York: American Vacuum Society, 2002), 52–54.

2. W Besling et al., "Characterization of TiN Films Deposited by Atomic Layer Deposition," in Proceedings of the Third International Conference on Microelectronics and Interfaces (New York: American Vacuum Society, 2002), 56–58.

3. W Besling et al., "Atomic Layer Deposition of Barriers for Interconnect," in Proceedings of the 2002 International Interconnect Technology Conference (Piscataway, NJ: IEEE, 2002), 288–291.

4. G Beyer et al., "Development of Sub-10-nm Atomic Layer Deposition Barriers for Cu/Low-k Interconnects," to be published in Microelectronic Engineering.

5. A Satta et al., "Enhancement of ALCVD TiN Growth on Si-O-C and α-SiC:H Films by O²-Based Plasma Treatments," Microelectronic Engineering 60 (2002): 59–69.

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Gerald Beyer, PhD, is the program manager of the copper/low-k industrial affiliation program at the Interuniversity Microelectronics Center (IMEC) in Leuven, Belgium. He joined the research center in 1994 and has worked in the fields of interconnect technology and semiconductor materials analysis. After studying chemistry in Leipzig, Germany, Beyer obtained an MSc in materials science (1991) from Thames Polytechnic, London, and a PhD (1994) from Imperial College of Science, Technology, and Medicine, London. (Beyer can be reached at +32 16 281211 or gerald.beyer@imec.be.)

Mieke Van Bavel, PhD, is a scientific editor at IMEC. She is jointly responsible for authoring and editing the research organization's numerous company technical documents and publications. She received a PhD in physics from the Catholic University of Leuven, Belgium. (Van Bavel can be reached at +32 16 281211 or vanbavel@imec.be.)