STRAINING FOR EFFECT: The 90-nm transistor uses strained-silicon technology to speed the flow of electrons. MICROGRAPHS COURTESY OF INTEL

Waving off the industry's woes, Intel announced plans August 13 to roll out its most advanced process technology for volume chip manufacturing next year. The leading semiconductor manufacturer says it will combine its 90-nm process with successful "technology breakthroughs" in a single 300-mm wafer process.

Either brave or foolhardy, the decision enables Intel to keep to its schedule of introducing new technology every two years. On the upside, Intel believes the investment will put it in a position to benefit from an anticipated industry recovery in two years. The downside, of course, is that the chipmaking giant will be saddled with excess capacity and a poor balance sheet should the slump drag on.

The integrated process combines strained-silicon processing, copper interconnects, and new low-k dielectric materials with high-performance, low-power transistors. Intel claims it's the first time the technologies have been used in one manufacturing technique. The company says the technique has been "routinely" processing wafers with good yields at D1C, its 300-mm development fab, in Hillsboro, OR.

The transistors in Intel's 90-nm process have gate lengths of 50 nm, making them the smallest CMOS transistors in the industry, Intel boasts. The chipmaker notes that its commercial Pentium 4 microprocessors have 60-nm gate lengths. To increase transistor speed, the gate oxides measure just five atomic layers, or 1.2 nm, thick.

THIN: Intel's process uses gate oxides measuring 1.2 nm, or approximately five atomic layers.

Waiting also in Intel's wings for volume production in 2003 are strained-silicon technology and copper interconnects. The copper process uses a new carbon-doped oxide dielectric that increases the chip's signal speed and lowers power consumption. The dielectric's two-layer stack design is easy to manufacture, Intel says. The process features seven copper interconnect layers using a combination of 248- and 193-nm-wavelength lithography.

Strained-silicon technology has received a lot of attention lately in the industry. IBM's T. J. Watson Research Center announced breakthroughs with the technology last year. The strained-silicon process speeds electron flow by stretching the placement of silicon atoms. The smooth current flow increases transistor speed. Intel will be the first to use the technique in volume production. The chipmaker has already used the 90-nm process to make SRAM devices with the industry's highest capacity of 52 Mb and a cell size measuring only 1 µm².

The cost of the volume ramp-up will be minimized because the company will use approximately 75% of the tools now in use for processing 130-nm chips on 300-mm wafers, Intel points out. After transferring the technology from D1C, Intel says three fabs will be using the 90-nm process by 2003, and the chipmaker will introduce a microprocessor with the code name "Prescott" by the second half of the year. Prescott is based on Intel's NetBurst microarchitecture.

In making the announcement, Sunlin Chou, Intel's senior vice president and general manager of the company's technology and manufacturing group, chided competitors for their slow transition to 130-nm processes on 200-mm wafers. Whether the decision spearheaded by CEO Craig Barrett is the bold move the company claims, or a leap into the void, remains to be seen, of course.

Chou trumpeted the company line. "We are moving ahead with the most advanced 90-nm technology exclusively on 300-mm wafers. This combination will allow Intel to make better products and reduce manufacturing costs."

A lead story on strained-silicon technology appeared in the Industry News section of MICRO, May 2002.