Edit Braunstein, Daniele Gilkes, Steven Lippy, Stephen Reid, and Ricky Adebanjo, Agere Systems

A series of in-house experiments demonstrates that methods for reclaiming copper control wafers involving CMP or a universal chemistry can restore wafers to near-pristine condition.

During the development of 0.12- and 0.13-µm copper devices, it is imperative to use clean silicon wafers to monitor and characterize defects arising from processes and process tools, improvements, or modifications. Defects greater than 0.12 µm in size can compromise the integrity of multilevel metal interconnect stacks by causing failures such as shorts or opens within the metal lines of the circuit, which affect device operation.¹ The only way to isolate particle contamination to a specific tool or process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroplating, is to use clean wafers to monitor process stability. Using silicon monitor wafers with small enough (<0.12-µm) and few enough defects prevents confounding defects caused by earlier processes with those caused by subsequent dielectric, copper barrier, or copper thin-film deposition processes.

Many control wafers are needed for process definition, verification, validation, and transfer. Consequently, reclaiming and reusing control wafers is essential for reducing material consumption and costs. At the same time, it is also essential to maintain wafer quality throughout the reclaim process.

However, few vendors are willing to reclaim copper wafers because the reclaim process involves the high risk of copper cross-contamination. Moreover, the traditional mechanical and chemical processes used by many reclaim vendors may have contamination implications. For example, the use of chemical immersion baths during wafer reclaim increases copper concentration and the possibility of copper deposition on the silicon surface. Solid copper removed from the surface of the wafer forms copper ions in the chemical bath, which can easily diffuse into the bulk of the silicon from either the front or backside of the wafer. That process is accelerated when the removal chemistries are used at high temperatures.

An alternative approach to chemical processing involves the use of mechanical processes such as chemical-mechanical polishing (CMP), but such processes also have a downside. Because CMP cannot round the edge of the wafer, residual copper contamination remains. To overcome that issue, some vendors have developed chemistries that chelate the copper in solution to avoid the deposition of copper onto the silicon surface.²

Copper Contamination Issues

The use of copper as the new interconnect material for circuits has posed many challenges to semiconductor engineers. One of them is the development of efficient diffusion barriers for copper interconnects. These barriers, which can be deposited by both PVD and CVD processes, are being developed to stop copper diffusion. The possibility of metal contamination during front-end manufacturing has prompted the industry to create strict protocols for handling wafers after copper deposition in different areas of the cleanroom, as well as in production and metrology tools. Isolated bays have been designated for copper operations, while copper processing generally takes place in dedicated tools. Although some tools are used to process both copper and noncopper wafers, they require special cleaning to prevent copper cross-contamination and must be monitored for the presence of trace metals.

The extremely high diffusivity of copper in silicon, a consequence of its small ionic radius and its relatively weak interaction with the silicon lattice, makes the metal highly mobile at room temperature. When copper interacts with silicon, the main types of defect reactions include the formation of point defects and their complexes, the formation of copper salicide precipitates in the bulk, and the decoration of existing extended defects, such as the dislocation of grain boundaries.³ Copper forms high-density precipitates in the wafer bulk, especially when the wafer is rapidly cooled or quenched. Point defects reduce the silicon's minority carrier lifetime. In addition, copper can outdiffuse to the surface and aggregate, which affects silicon oxide growth. In short, copper control wafers should be reclaimed to avoid any chance that copper will contaminate the bulk or surface of the silicon.

Outsourcing the Reclaim Process

Agere Systems' development facility in Orlando, FL, requires large quantities of silicon control wafers for process development and control. While processes that will be used to form multilayer metal interconnect stacks are being optimized, monitor wafers with various metal and dielectric thicknesses are being produced. As a result of this procedure, control/test wafers are produced with layers that have different constitutions and thicknesses. Consequently, a universal reclaim process is needed. The wafers that must be stripped back to bare silicon have a variety of films:

* Electroplated copper, from angstroms to many microns thick.
* Seed copper of angstrom thicknesses.
* Metal barriers composed of tantalum, tantalum nitride, and combinations of both.
* Repeated layers of tantalum nitride/copper at different thicknesses.
* Different types of oxides at different thicknesses.
* PTEOS and silane oxides deposited on different tools.
* Low-k dielectric materials such as SiLK and Coral.

In most cases, the thickness of the barrier layer and metal are not known, posing an additional challenge to the copper wafer reclaim process. And in some cases, the type of metal barrier and the deposition order are unknown.

The research team at Agere turned to two vendors to reclaim copper/low-k control wafers.

Vendor 1. Although this vendor did not have a copper reclaim process in production, Agere researchers investigated the vendor's ability to reclaim noncopper wafers with acceptable defect levels. In order to evaluate the potential quality of the vendor's output, data from reclaimed noncopper wafers were analyzed, leading to the conclusion that the specifications needed for the development of 0.13-, 0.12-, or 0.10-µm technologies were not satisfied.

Defects on the reclaimed noncopper wafers were first measured using a 6200 tool from KLA-Tencor (San Jose), a standard instrument for performing defect measurements at 0.16- and 0.20-µm technology nodes. The same wafers were later measured with a KLA-Tencor SP1 Surfscan, a tool designed to qualify reclaimed copper wafers. (Since the SP1's illumination and collection optics have better sensitivity and more-accurate particle sizing capability than the KLA-Tencor 6200 or 6400, it will eventually become the tool of choice for performing measurements at <0.30-µm technology nodes.) Figure 1 indicates that only 18% of the wafers returned from the vendor passed the specification limit for reclaim wafers used to develop new technologies (<50 0.2-µm defects).

Figure 1: Counts of >0.2-µm defects on reclaimed control wafers from vendor 1, as detected by two different analysis tools (18% of the wafers had <50 defects/wafer and 42% had <100 defects/wafer).

Vendor 2. In contrast to vendor 1, vendor 2 offered a process to reclaim copper control wafers. Although that process resulted in minimum numbers of defects, SP1 measurements detected haze a few weeks after the wafers returned from the reclaim facility. The defects were analyzed using a variety of analytical techniques. First, SEM images showed large numbers of uniform circular particles. Those particles were then subjected to Auger analysis and determined to be copper. Figure 2a shows an SEM image of one such defect, and Figure 2b shows that defect's respective Auger spectrum.

The copper defects were assumed to have originated in the bulk of the silicon, which probably was contaminated during the hot-acid strip process. Copper then diffused back to the surface of the silicon, resulting in the uniform defects seen in the SEM image. Since a polished wafer surface is hydrophobic and extremely reductive because of dangling and silicon-hydrogen bonds, it is possible that copper cations (Cu⁺/Cu⁺⁺) were being reduced by the surface of the silicon, causing an outplating reaction of copper dissolved inside the wafer.

In-House Reclaim Studies

Based on an evaluation of the wafers returned from vendors 1 and 2, the Agere research team concluded that to obtain reliable reclaimed copper control wafers, it would be necessary to develop an internal reclaim process at the company's advanced development research facility. An effective process would have to be able to strip copper, metal barriers, and low-k dielectric films, and then return the wafer surface to a pristine condition while preventing bulk or surface copper contamination. Consequently, the team investigated several processes to strip copper control wafers, including ones involving the use of chemical cleaning tools. The investigations resulted in reclaimed wafers that did not diffuse copper to the bulk silicon and had minimal numbers of defects measuring 0.15 µm in size.

Tools Used to Perform Reclaim Studies. A spray tool with a single-use chemistry was identified as the initial tool to perform the reclaim work. The tool's capabilities and cleaning efficiency were demonstrated by reclaiming oxide control wafers. As shown in Figure 3, the tool's particle-removal efficiency was excellent. Other tools used for this work included a single-wafer cleaning tool and a scrubber with megasonics capability. Although the intended purpose of these tools was to process the 0.13-µm devices then in development, they were identified as being of use in the copper-wafer reclaim project.

Figure 3: Counts of 0.15-µm particles before and after oxide control wafers were cleaned in the spray tool.

During the development of metal strip and silicon surface-conditioning operations, many systematic studies were conducted. These studies resulted in several different processes, three of which are described below.

Process 1: Reclaim Process Using CMP. Process 1 involved the reclaim of copper control wafers that had a 6-kÅ- to 2-µm-thick layer of electroplated copper on a PVD- deposited copper seed layer with an underlying copper-diffusion barrier layer of an unknown type. A recipe was formulated in the clean spray tool to strip such a thick layer of copper. The barrier layer was then polished using CMP. Subsequently, the underlying oxide films and the barrier layer that remained on the bevel edge after CMP were stripped in the spray tool using a combination of chemicals. The next step used a scrubber to loosen any remaining particles. Figure 4 describes the process and Figure 5 shows the posttreatment distribution of particles on the silicon wafers. The reclaim control wafers emerging from these process steps had relatively few defects.

Figure 4: Procedure for reclaiming copper control wafer with unknown metal barriers using CMP (process 1).

Process 2: Reclaim Process Using a Universal Chemical. Although process 1 can reclaim copper control wafers with acceptable defect levels, the use of CMP to strip the unknown barrier layer is expensive. Moreover, many wafers available for reclaim have multiple combinations of copper and metal barrier layers, which can complicate the use of CMP for removing the barrier metal. The CMP process is also selective and dependent on metal type and thickness.

A robust alternative to CMP is the use of a universal chemical that etches all metals while slowing or stopping the reaction rate at the oxide layer. Many chemicals or chemical mixtures can be used to achieve that objective. Accordingly, the Agere team investigated several different chemicals, characterizing their etch rate, selectivity, and uniformity to determine the optimum one for reclaiming various multilayer metal stacks. The chemistry selected offers a high etch rate for copper and the copper barrier layer (composed of tantalum and tantalum nitride) and a very low etch rate for the oxide film.

The downside of using that chemistry is that it can damage the silicon surface. While the oxide film protects the front side of the wafer, the backside is sometimes unprotected. In such cases, the stripping process can damage the wafer and ultimately affect wafer flatness. Also, an exposed wafer backside can be contaminated by diffused copper during etching. Consequently, the wafer backside must be protected by a film that is inert or has low reactivity to the reclaim chemistry, or it must be protected by the tool in which the wafer is processed. The research team opted for the second alternative: etching the copper wafers in a single-wafer process tool in which the wafer backside is protected while the wafer spins on a chuck and a moving arm suspended above the wafer dispenses the chemistry.

Preliminary trials showed that after the metals and oxide film had been removed using the single-wafer tool followed by the spray cleaning tool, an area close to the wafer center had a high density of defects, which were identified as pits. Further investigations revealed that the defects resulted from the oxide postmetal strip process. SEM inspections identified small particles in the same area where the pits were found. After undergoing Auger analysis, those particles were discovered to be composed primarily of copper, as illustrated in the top part of Figure 6.

In order to determine whether the particles were residues from a nonetched zone in the wafer or were deposited while the chemical reaction took place, the research team sputtered the particles for several minutes and analyzed their composition. The bottom part of Figure 6 shows that after 10 minutes of sputtering, tantalum was found in the particle core, indicating that an etch dead area was present in the wafer. The copper left on the oxide during oxide removal was responsible for the silicon pits (known as metal-induced pitting).⁴ In order to etch the entire metal surface of the wafer and prevent such defect occurrences, the chemical dispense arm was programmed to perform a combination of movements affecting the position of the arm above the wafer and arm speed. In addition, a precleaning step was introduced on the spray tool before oxide removal.

Process 3: Reclaim of Copper Control Wafers and Low-k Dielectric Films. In process 3, the metal films were removed as in process 2, but new recipes were developed on the spray tool for each type of low-k dielectric film. Additional surface conditioning included the use of a scrubber, megasonic energy, and a final silicon surface clean.

Conclusion

The reclaim of copper/low k multilevel metal-stacked control wafers for the development of 0.13-µm and smaller copper semiconductor technologies requires a highly robust method. Throughout the development process discussed in this article, multilevel metal interconnect film stacks, consisting of copper and copper barrier materials such as tantalum and tantalum nitride, and low-k materials such as SiLK and Coral were changing in composition and thickness. Therefore, a universal method was required to remove those layers while restoring the wafer surface to the quality of a prime substrate and preventing copper cross-contamination of the surface and bulk of the silicon.

Several processes were developed and tested. A multistep procedure using available tools was determined to be optimal for treating wafers with diverse types of layers while ensuring wafer quality and preventing copper contamination.

Figure 7: Surfscan analyses revealing that 78% of the reclaimed copper control wafers had <50 0.2-µm defects (a) and <100 0.15-µm defects (b).

As shown in Figures 7a and 7b, that low-cost procedure was used to process at least four cycles of wafers with excellent results. Analyses using the Surfscan SP1 tool revealed that 78% of the wafers had <50 0.2-µm defects and <100 0.15-µm defects. The yield from the in-house reclaim process was significantly higher than that from the two vendors discussed here, who also performed a final polish of the wafer surface. Adding a final polishing step to the in-house process would have further improved wafer yield.

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References

1. Y Nishi and Robert Doering, Handbook of Semiconductor Manufacturing Technology (Monticello, NY: Marcel Dekker, 2000).

2. C Beaudry, S Takada, and T Suzuki, "Evaluating Wafer Reclaim Techniques in Emerging Copper Processes," MICRO 18, no. 3 (2000): 41–54.

3. A Istratov and E Weber, "Physics of Copper in Silicon," Journal of the Electrochemical Society 149, no. 1 (2002): G21–G30.

4. H Morinaga, M Suyama, and T Ohmi, "Mechanism of Metallic Particle Growth and Metal Induced Pitting on Si Wafer Surface in Wet Chemical Processing," Journal of the Electrochemical Society 141, no. 10 (1994): 2834–2841.

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Edit Braunstein is a member of the technical staff in the Bell Labs/VLSI process development department of Agere Systems (Orlando, FL). She is responsible for the development and optimization of wet clean/etch processes in front-end-of-line and back-end-of-line processes. She joined Bell Labs in 2000 after 14 years at Eastman Kodak. She received a degree in chemical engineering from the Universidad Nacional del Litoral in Santa Fe, Argentina, and an MS in chemical engineering from Technion (Israel Institute of Technology) in Haifa. (Braunstein can be reached at 407/371-6663 or elb4@agere.com.)

Daniele Gilkes worked on copper electroplating processes and associated metrology techniques at Agere Systems. She is experienced with design of experiment methodologies and statistical methods of control. She received a BS in chemical engineering from the University of Florida in Gainesville.

 

 

Steven Lippy has been an engineer in the yield enhancement group at Agere Systems for the past four years. He is the process engineer in charge of all unpatterned-wafer inspection tools and process-tool monitoring techniques. Previously, he served two years as a member of the plasma etch and PECVD process teams at Agere in Allentown, PA. He received a BS in chemical engineering from the University of Pittsburgh. (Lippy can be reached at 407/371-3144 or slippy@agere.com.)

 

Stephen Reid was a senior technical associate in the Bell Labs/VLSI process development department at Agere Systems. His responsibilities included tracking equipment performance metrics, generating tool enhancement, and sustaining and developing back bevel-edge copper removal processes. Previously he worked at Motorola in the semiconductor product sector. He studied electrical and electronic engineering at Glasgow College of Technology in Glasgow, Scotland, and has a bachelors degree.

 

Ricky Adebanjo, PhD, is the technical manager for Cu-CMP and chemical cleans in the Bell Labs/VLSI process development department at Agere and has held various positions since joining the company as a member of the technical staff in 1995. He received a PhD in materials science and engineering from Stanford University in Palo Alto, CA. (Adebanjo can be reached at 407/371-7497 or adebanjo@agere.com.)