More than 10 years ago, however, researchers discovered that patterns, such as IC devices, within a wafer could induce temperature variations.¹ Known as the pattern effect, this phenomenon has been confirmed both by theoretical calculations and experimentally. It results from the differential coupling of optically dense regions of the wafer to the heat source used in RTP. Typically, denser areas such as logic sections absorb and emit radiation more quickly than less-dense areas such as memory sections. Depending on the specific wafer pattern, the process, and the design of the RTP system, temperature variations of as much as 40°C can occur.² This magnitude of variation is much greater than the level deemed acceptable in The International Technology Roadmap for Semiconductors, which specifies within-wafer temperature variations of 2°–3°C (at 3s) for the 130-nm technology node and beyond.³

Several new RTP system designs promise to mitigate the pattern effect on thermal uniformity. After describing the phenomenon in some detail, this article focuses on the use of lower-temperature heat sources such as hot walls instead of lamps. Results of steady-state calculations, experiments with test patterns, and measurements taken on lots split between hot-wall and lamp-based RTP systems confirm that the pattern effect is less severe on wafers processed in a hot-wall system.

Pattern effect temperature nonuniformity is caused by variations in total broadband absorptivity and emissivity across the wafer which arise in the nonisothermal environment of a typical RTP system, where the wafer is not at the same temperature as its surroundings. From the literature, which presents both modeling and experimental data, it is known that the pattern effect is most severe with single-side heating on the wafer's patterned side and a heating environment that is far from thermal equilibrium.⁴ Conversely, the ideal environment is heating both sides of the wafer with a heat source that is as close as possible to the temperature of the wafer. Figure 1 illustrates the basic behavior of the pattern effect phenomenon for different RTP environments.

Figure 1: Basic behavior of the pattern effect phenomenon for different RTP environments. The pattern effect is most severe for wafers heated on only one side in an environment that is far from thermal equilibrium.

In traditional RTP tools, the energy source is a bank of tungsten halogen lamps that reach a temperature of 2000°C or higher while the process chamber walls remain relatively cool at <400°C. Process temperatures on the wafer are typically between 500° and 1100°C, and heat transfer is dominated by thermal radiation from the lamps to the wafer and from the wafer to the chamber walls.

The large temperature differences enable the fast wafer heating and cooling and the remarkable flexibility of process control that are characteristic of RTP. However, because the optical properties of the wafer affect both its absorption of energy from the lamps and emission of energy to the chamber, coatings or patterns on the wafer surfaces lead to across-wafer temperature variations.⁵ For example, even a very simple coating, consisting of a layer of polysilicon on top of a thin silicon dioxide film, can cause the lamp power coupling to vary from 0.4 to 0.8, depending on the thickness of the two constituent films. There is a similar impact on the integrated thermal emissivity, which determines how much the wafer radiates to the chamber walls.

If a coating is present only on parts of the wafer, then the uncoated regions will experience different temperature-time cycles during processing than the coated regions, which can have a significant impact on process uniformity. Thus, it is essential for RTP systems to include closed-loop wafer-temperature control capability. This can be achieved with an integral pyrometer that measures the wafer temperature and provides feedback to the control system. The challenge is to perform highly accurate pyrometric measurements on a wafer of unknown spectral emissivity in surroundings where a large amount of stray radiation may be emitted by the heat source. Suppliers of RTP tools have addressed that challenge using various innovative techniques, which, when combined with sophisticated power control, have led to excellent temperature results on monitor wafers. It is important to realize, however, that a closed-loop temperature control system can correct for the effects of coatings only in the regions adjacent to where wafer temperatures are being measured.

Areas with different radiative properties must be farther than ~1–2 mm apart for the pattern effect to be significant. For smaller-length scales, conduction in the silicon substrate will smooth out any temperature variation. Based on the values for the conductivity of silicon (1.4 W/cm/°C), the thickness of a typical 300-mm wafer (750 µm), and the heating power delivered to the wafer surface from the radiative environment (~30 W/cm²), the relaxation distance for conduction is ~1 mm. This limitation on distance means that small devices will not cause significant temperature nonuniformity.

On the other hand, larger die such as those used for a system-on-a-chip or combined logic and memory circuits will tend to create large across-wafer temperature variations. The effects of such variability have been simulated by other researchers using a linearized heat-conduction model with radiation.² Those results indicated that a 10% change in thermal absorptivity over a distance of 50 mm or greater will lead to a temperature shift of almost 40°C. Even for structures as small as 5 mm, the temperature difference can be approximately 12°C with a 10% change in absorptivity.

To understand the pattern effect mathematically, consider a segment of a wafer with different optical properties in different regions such as the one shown in a simplified sketch in Figure 2. A steady-state heat balance in area 1 can be expressed as

If there is thermal equilibrium in the system, then a_f,1 = e_f,1 and a_f,2 = e_f,2. This situation is approached most closely when the heat source is nearly the same temperature as the wafer. If there is heating from both sides of the wafer, then Q_inc, _f = Q_inc, _b. When both conditions are met—that is, when there is thermal equilibrium and heating occurs on both sides of the wafer—then across-wafer temperatures will be uniform: T₁ will equal T₂.

Total, or broadband, emissivity (e_tot) and absorptivity (a_tot) are obtained by integrating over all wavelengths, using the equations

and

If T_source ≈ T_w, (close to thermal equilibrium), then a_tot ≈ e_tot, and the pattern effect will be minimal. If T_source ≠ T_w, then a_tot ≠ e_tot, and temperature nonuniformity will occur.

Neither lamp systems nor hot-wall systems achieve perfect thermal equilibrium—there must be some difference between the source temperature and the wafer temperature in order to heat the wafer. However, with lamp systems, the divergence from an isothermal environment is much greater. In hot-wall systems, the maximum and minimum wall temperatures are typically 1200°C and ~800°C, respectively, for a process running at 1000°C. By contrast, in a lamp-based system the temperature of the lamps for a similar process is ~2300°C while the chamber walls are ~400°C.

Because the temperature of the heat source has to be much higher than the wafer temperature, the source's emission spectrum is very different from the spectrum radiated from the wafer. Wien's law states

Effects of a Hot Liner. The pattern effect has been studied using a modified lamp-based system capable of double-sided heating.⁶ For some test runs a hot liner was placed in the chamber to act as a shield between the patterned side of the wafer and the lamps, thereby converting the radiated heat to a longer wavelength. Experimental thermocouple wafers with a chessboard-like pattern of alternating Si₃N₄ and Si regions were processed at 1070°C for 30 seconds, with stabilization at 750°C and a ramp-up rate of 50°C/sec. (With the additional mass of the liner in the heating chamber, a slow ramp-up rate was required to maintain uniformity. It would not be possible to use the system for USJ formation with such a slow rate.) The temperatures of the two types of region were measured and the average difference between them was determined.

The results, summarized in Table I, indicate that pattern-effect temperature differences for lamp systems with a direct line of sight between the wafer and the lamps can be relatively large; they approached 30°C when only the top lamps were used and 15°C when both top and bottom lamps were on. When a simulated hot-wall environment was created by using the liner, however, the temperature difference was <5°C.

Hot-Wall System Performance. Experiments with a hot-wall system also have demonstrated such tools' ability to minimize temperature nonuniformity. The Summit system from Axcelis Technologies (Beverly, MA) used in the testing provides an essentially isothermal environment around all sides of the wafer. Its ramp-up and cooldown rates depend only on moving the wafer in and out of the hot environment. Because the chamber walls are not cooled between every wafer cycle, there is a low potential for warpage and associated wafer contamination. The walls have been tested in N₂, O₂, NH₃, and steam environments with no signs of deterioration. Two chip manufacturers in the United States and one in Japan have been using the tool successfully in production environments.

Table II shows the results of an experiment comparing the hot-wall system with a lamp-based system. These tests were conducted at one device manufacturer's fab using monitor wafers and split lots of 200-mm product wafers. Each wafer was exposed to a 10-second source-drain-soak-anneal cycle at approximately 1000°C, after which temperature uniformity on the monitor wafers was measured with a four-point probe and product wafer uniformity was determined by measuring the variability of the contact resistance.

Both systems showed good within-wafer uniformity for the monitor wafers. The variation amounted to less than 1°C (1 s), in line with expectations derived from The International Technology Roadmap for Semiconductors. Product wafers processed in the lamp-based system exhibited greater variability than those processed in the hot-wall tool, suggesting that there had been a pattern effect with the former system.

Another experiment conducted at an IC manufacturer's fab using split lots measured overlap capacitance on wafers processed in the hot-wall system and others processed in a lamp-based tool. Both soak anneals of 5–10-second duration and spike anneals of a nominal 2-second duration were performed on the wafers at process temperatures of approximately 1000°C. It is clear from the results, shown in Figure 3, that the hot-wall system gave consistently lower ranges of overlap capacitance than the lamp-based system did.

Figure 3: Comparative overlap capacitance measurements on product wafers processed in RTP systems using lamp or hot-wall heat sources.

The slightly nonisothermal environment of the hot-wall system will also produce some nonuniform temperature effects, however, as was shown by a demonstration at Axcelis using an experimental 200-mm wafer with a checkerboard pattern consisting of squares of 90-mm-thick TEOS. The wafer was processed at 1050°C in a spike anneal with a thermal budget of approximately 2 seconds, which is characteristic of USJ formation cycles. A pattern effect of modest magnitude can be seen in Figure 4, which plots the variation of sheet resistance as measured by a four-point probe. With a sensitivity of approximately 1 W/sq/°C, the range of temperature variation was 8°C, in line with the results seen earlier in the experiments involving a lamp-based system with a hot liner.⁴ Further improvements may be possible with RTP systems that rely on conduction rather than radiation to achieve wafer heating. At least one such system is under development.

Figure 4: Sheet-resistance variation on a checkerboard-patterned wafer processed in a hot-wall RTP system.

Conclusion

The pattern effect caused by emissivity and absorptivity variations in the nonisothermal environment of RTP systems can lead to significant deviations from a uniform temperature distribution across the processed wafer. As device sizes increase, this effect will become more significant, since larger devices do not benefit from the conduction in the substrate that smooths out variations when features are less than 1–2 mm apart. While wafer heating by radiation, the dominant method in RTP, will always result in some pattern effect, techniques such as heating the wafer from both sides, adding devices such as a hot liner to lamp-based systems, and designing systems that use hot walls as the heat source can mitigate that effect. The experimental results presented here demonstrate that a hot-wall system can offer an advantage over lamp-based systems by minimizing pattern effect temperature nonuniformity.